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CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (
μ
PD78018F SUBSERIES)
(b) Serial bus interface control register (SBIC)
SBIC is set by a 1-bit or 8-bit memory manipulation instruction.
This register is set to 00H when the RESET signal is input.
Note
Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.
Remarks 1.
Bits 0, 1, and 4 (RELT, CMDT, ACKT) are 0 when they are read after data has been set.
2.
CSIE0: Bit 7 of the serial operation mode register 0 (CSIM0)
<6>
<5>
<4>
<3>
<2>
<1>
<0>
<7>
Symbol
SBIC
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
RELT
Used to output bus release signal.
SO0 latch is set to 1 when RELT = 1 . Atter setting SO0 latch, RELT is automatically cleared to 0.
This bit is also cleared to 0 when CSIE0 = 0.
R/W
FF61H 00H R/W
Note
Address On reset R/W
CMDT
Used to output command signal.
SO0 latch is cleared to 0 when CMDT = 1 . After clearing SO0 latch, CMDT is automatically cleared to 0.
This bit is also cleared to 0 when CSIE0 = 0.
R/W
R
RELD
Bus release detection
Setting condition (RELD = 1)
Clearing conditions (RELD = 0)
When bus release signal (REL) is detected
When transfer start instruction is executed
When values of SIO0 and SVA do not coincide
when address is received
When CSIE0 = 0
When RESET is input
R
CMDD
Command detection
Clearing conditions (CMDD = 0)
When transter start instruction is executed
When bus release signal (REL) is detected
When CSIE0 = 0
When RESET is input
Setting condition (CMDD = 1)
When command signal (CMD) is detected
ACKT
Outputs an acknowledge signal in synchronization with the falling edge of the SCK0 clock immediately after
the instruction that sets this bit to 1 has been executed, and then is automatically cleared to 0.
Used as ACKE = 0.
This bit is also cleared to 0 when transfer of serial interface is started or when CSIE0 = 0.
R/W