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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
μ
PD780058Y Subseries)
(4) Various signals
A list of signals in the I
2
C bus mode is given in Table 17-4.
Table 17-4. Signals in I
2
C Bus Mode
Signal name
Description
Start condition
Definition :
Function :
Signaled by :
Signaled when :
Affected flag(s) :
Definition :
Function :
Signaled by :
Signaled when :
Affected flag(s) :
Definition :
Function :
Signaled by :
Signaled when :
Affected flag(s) :
Definition :
Function :
Signaled by :
Signaled when :
Affected flag(s) :
Definition :
Function :
Signaled by :
Signaled when :
Affected flag(s) :
Definition :
Function :
Signaled by :
Signaled when :
Affected flag(s) :
Definition :
Function :
Signaled by :
Signaled when :
Affected flag(s) :
Definition :
Function :
Signaled by :
Signaled when :
Affected flag(s) :
SDA0 (SDA1) falling edge when SCL is high
Note 1
Indicates that serial communication starts and subsequent data are address data.
Master
CMDT is set.
CMDD (is set.)
SDA0 (SDA1) rising edge when SCL is high
Note 1
Indicates end of serial transmission.
Master
RELT is set.
RELD (is set) and CMDD (is cleared)
Low level of SDA0 (SDA1) pin during one SCL clock cycle after serial reception
Indicates completion of reception of 1 byte.
Master or slave
ACKT is set with ACKE = 1.
ACKD (is set.)
Low-level signal output to SCL
Indicates state in which serial reception is not possible.
Slave
WAT1, WAT0 = 1x.
None
Synchronization clock for output of various signals
Serial communication synchronization signal.
Master
See
Note 2
below.
CSIIF0. Also see
Note 3
below.
7-bit data synchronized with SCL immediately after start condition signal
Indicates address value for specification of slave on serial bus.
Master
See
Note 2
below.
CSIIF0. Also see
Note 3
below.
1-bit data output in synchronization with SCL after address output
Indicates whether data transmission or reception is to be performed.
Master
See
Note 2
below.
CSIIF0. Also see
Note 3
below.
8-bit data synchronized with SCL, not immediately after start condition
Contains data actually to be sent.
Master or slave
See
Note 2
below.
CSIIF0. Also see
Note 3
below.
Stop condition
Acknowledge signal (ACK)
Wait (WAIT)
Serial clock (SCL)
Address (A6 to A0)
Transfer direction (R/W)
Data (D7 to D0)
Notes 1.
The level of the serial clock can be controlled by bit 3 (CLC) of interrupt timing specify register
(SINT).
2.
Execution of instruction to write data to SIO0 when CSIE0 = 1 (serial transfer start directive). In
the wait state, the serial transfer operation will be started after the wait state is released.
3.
If the 8-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 8th clock cycle
of SCL. If the 9-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 9th
clock cycle of SCL. CSIIF0 is set if an address is received and that address coincides with the
value of the slave address register (SVA) when WUP = 1, or if the stop condition is detected.