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APPENDIX C INDEX
422
Clock generator (CG) ---------------------------------------30
Clock output function --------------------------------------140
Command register -------------------------------------------88
Communication command -------------------------------402
Communication reservation -----------------------------275
Communication system ----------------------------------396
CORAD0 to CORAD3 -------------------------------------393
CORCN -------------------------------------------------------392
Correction address registers 0 to 3 -------------------393
Correction control register -------------------------------392
Correction request register ------------------------------393
CORRQ -------------------------------------------------------393
CPU -------------------------------------------------------------30
CPU address space -----------------------------------------63
CPU register set ----------------------------------------------58
CR20 to CR70 ----------------------------------------------189
CR23, CR45, CR67 ---------------------------------------202
CRC0, CRC1 ------------------------------------------------161
CRn0 ----------------------------------------------------------156
CRn1 ----------------------------------------------------------157
CSI0 to CSI3 ------------------------------------------------219
CSI4 -----------------------------------------------------------310
CSIB4 ---------------------------------------------------------314
CSIC0 to CSIC4 ------------------------------------- 123, 124
CSIM0 to CSIM3 -------------------------------------------221
CSIM4 ---------------------------------------------------------313
CSIS0 to CSIS3 --------------------------------------------221
[D]
Data wait control register ----------------------------------93
DBC0 to DBC5 ----------------------------------------------343
DCHC0 to DCHC5 -----------------------------------------343
DIOA0 to DIOA5 --------------------------------------------341
DMA function -----------------------------------------------341
DMA byte count registers 0 to 5 -----------------------343
DMA channel control registers 0 to 5 -----------------343
DMA internal RAM address registers 0 to 5 --------342
DMA peripheral I/O address registers 0 to 5 --------341
DMAIC0 to DMAIC5 -------------------------------- 123, 124
DRA0 to DRA5 ----------------------------------------------342
DSTB ------------------------------------------------------------48
DWC -------------------------------------------------------------93
[E]
ECR -------------------------------------------------------------60
EGN0 --------------------------------------------------- 115, 359
EGP0 --------------------------------------------------- 115, 359
EIPC -------------------------------------------------------------60
EIPSW --------------------------------------------------------- 60
Error detection ---------------------------------------------- 271
EV
DD
------------------------------------------------------------51
EV
SS
-------------------------------------------------------------51
Exception trap ---------------------------------------------- 131
Extension code --------------------------------------------- 271
External expansion mode ---------------------------------73
External memory ---------------------------------------------71
External wait function ---------------------------------------94
[F]
Falling edge specification register --------------115, 359
FEPC -----------------------------------------------------------60
FEPSW ---------------------------------------------------------60
Flash memory ---------------------------------------------- 395
Flash memory control ------------------------------------ 401
Flash memory programming mode -------------- 62, 401
[G]
General register ----------------------------------------------59
[H]
Half-word access --------------------------------------------91
HALT mode ------------------------------------------------- 144
Handling of unused pins -----------------------------------52
Hardware start ---------------------------------------------- 323
HLDAK ---------------------------------------------------------48
HLDRQ ---------------------------------------------------------48
[I]
I
I
I
IC ----------------------------------------------------------------51
IDLE mode -------------------------------------------------- 147
Idle state insertion function -------------------------------95
IIC clock select registers 0, 1 --------------------------- 240
IIC control registers 0, 1 --------------------------------- 232
IIC shift registers 0, 1 -------------------------------230, 241
IIC status registers 0, 1 ---------------------------------- 237
IIC0, IIC1 -----------------------------------------------230, 241
IICC0, IICC1 ------------------------------------------------ 232
IICCL0, IICCL1 --------------------------------------------- 240
IICIC1 ---------------------------------------------------123, 124
IICS0, IICS1 ------------------------------------------------- 237
Illegal op code ---------------------------------------------- 131
Image -----------------------------------------------------------64
In-service priority register ------------------------------- 125
2
C bus ------------------------------------------------------- 227
2
C bus mode -----------------------------------------227, 242
2
C interrupt request --------------------------------------- 250