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參數(shù)資料
| 型號(hào)： | ZR36067 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | AV PCI CONTROLLER |
| 中文描述： | 影音PCI控制器 |
| 文件頁數(shù)： | 34/48頁 |
| 文件大小： | 580K |
| 代理商： | ZR36067 |
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34
AV PCI CONTROLLER
13.22 Vertical Sync Parameters
This register contains the VSYNC parameters to be generated
by the
ZR36067
as a sync master.
13.23 Horizontal Sync Parameters
This register contains the HSYNC parameters to be generated
by the
ZR36067
as a sync master.
13.24 Field Horizontal Active Portion
This register contains the horizontal parameters of the active
portion of the processed field.
13.25 Field Vertical Active Portion
This register contains the vertical parameters of the active
portion of the processed field.
13.26 Field Process Parameters
This register contains the general parameters of the field
process.
13.27 JPEG Code Base Address
This register specifies the base address of the code buffer table.
13.28 JPEG Code FIFO Threshold
This register specifies Code FIFO threshold in JPEG mode.
4 : 1
R
Reserved, Returns zero.
0
RW
all
Active
- This command bit is asserted by the
host in order to initiate a JPEG process.
‘1’ - Active is asserted.
‘0’ - Active is deasserted.
Default value is ‘0’.
Address Offset: 0x108
Bit
Type
Mod
Description
31: 24
RW
Reserved. Returns zero.
23: 16
RW
jpg
VsyncSize
- VSYNC signal length. The
VSYNC length is measured in lines.
Default value is 0x06.
15 : 0
RW
jpg
FrmTot
- Frame total size. The total number
of lines per frame. This parameter must be an
odd number.
Default Value is 0x020D (525, for NTSC)
Address Offset: 0x10C
Bit
Type
Mod
Description
31 : 16
RW
jpg
HsyncStart
- HSYNC signal Start point.
The point in the line (measured in number of
VCLKs) at which HSYNC should be asserted.
Default value is 0x0280 (640, for square pixel
NTSC).
15 : 0
RW
jpg
LineTot
- Line total size. The total number
VCLKs in a line.
Default Value is 0x030C (780, for square
pixel NTSC)
Address Offset: 0x110
Bit
Type
Mod
Description
31 : 16
RW
jpg
NAX
- The first pixel in a line to be processed.
Counted from the active edge of HSYNC.
Default value is 0x0000.
15 : 0
RW
jpg
PAX
- The number of pixels to be processed
in a line.
Default Value is 0x0280 (640, for square pixel
NTSC)
Address Offset: 0x104
Bit
Type
Mod
Description
Address Offset: 0x114
Bit
Type
Mod
Description
31 : 16
RW
jpg
NAY
- The first line in a field to be processed.
Counted from the active edge of VSYNC.
Default value is 0x000A.
15 : 0
RW
jpg
PAY
- The number of lines to be processed in
a field.
Default Value is 0x00F0 (240, for NTSC)
Address Offset: 0x118
Bit
Type
Mod
Description
31 : 1
R
Reserved. Returns zero.
0
RW
jpg
Odd_Even
- First field type. The type of the
first field to be processed. Odd type is defined
as the field in which the active edge of
VSYNC is asserted during the active portion
of the horizontal line. Even type is defined as
the field in which the active edge of VSYNC is
asserted during the active portion of HSYNC.
‘1’ - The first field is Odd.
‘0’ - The first field is Even.
Default value is ‘1‘.
Address Offset: 0x11C
Bit
Type
Mod
Description
31 : 0
RW
jpg
I_STAT_COM_PTR
- The memory address
of the code buffer table.
Default value 0xFFFFFFFC.
Address Offset: 0x120
Bit
Type
Mod
Description
31 : 8
R
Reserved, Returns zero.
7 : 0
RW
jpg
JPEGCodTrshld
- JPEG code FIFO Thresh-
old. In Compression, if the fullness level of
the Code FIFO (in doublewords) goes above
this threshold the PCI bus is requested.
In Decompression, if the fullness level of the
Code FIFO (in doublewords) goes under this
threshold the PCI bus is requested.
Default value is 0x50h
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZR36067PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
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| ZR36110PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Audio/Video Decoder for MPEG |
| ZR36120PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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