- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373821 > ZR36067 (Electronic Theatre Controls, Inc.) AV PCI CONTROLLER PDF資料下載
參數(shù)資料
| 型號： | ZR36067 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | AV PCI CONTROLLER |
| 中文描述： | 影音PCI控制器 |
| 文件頁數(shù)： | 29/48頁 |
| 文件大?。?/td> | 580K |
| 代理商： | ZR36067 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當(dāng)前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
29
AV PCI CONTROLLER
13.11 System, PCI and General Purpose Pins
Control Register
This register contains the software reset bit (byte 3), a PCI
control parameter (byte 2) and the General Purpose Pins direc-
tion parameter (byte 0).
13.12 General Purpose Pins and GuestBus Control
Register (I)
This register contains the values for General Purpose outputs
(byte 3) and timing parameters for the first four Guests (bytes
1-0).
13.13 MPEG Code Source Address Register
This register contains the DWORD base address for MPEG
mode code DMA transfers.
Address Offset: 0x028
Bit
Type
Mod
Description
31:25
R
Reserved. Returns zero.
24
RW
all
SoftReset
- Software Reset.
This bit is asserted by the host to reset the
ZR36067. If this bit is set to ‘0’ all resettable
registers in the device will be reset to their
default value, except:
- the SoftReset bit,
- the PCI interface.
The device continues to respond according to
the PCI Specification and can be the target of
a PCI transfer targeted at the ASRs or config.
space. The transfer (single- or burst-write)
asserting this bit will not be terminated abnor-
mally.
The device will not initiate any PCI transfers
during reset, because all DMA channels are
disabled.
This register continues to be programmable.
During reset, actually, only this bit of the
ASRs can be modified by the host (e.g.
turning reset off).
A power on (hardware) reset also asserts this
bit. After the hardware reset is over, a large
portion of the ZR36067 (see above) will
remain in reset mode until the SoftReset bit is
deasserted.
After this bit is deasserted, all registers retain
their default values, all DMA channels remain
disabled and all ASRs are programmable in
accordance with their modification condition.
‘1’ - no reset,
‘0’ - reset (default value after power on).
23:19
R
Reserved. Returns zero.
18:16
RW
all
WaitState
- PCI Wait State Control.
This parameter defines the number of wait
states inserted by the PCI slave logic. During
each PCI transfer cycle to the ZR36067, the
device will de-assert TRDY according to this
value.
Default value 000b.
15:8
R
Reserved. Returns zero.
7:0
RW
res
GenPurDir
- General Purpose Pins
Direction.
These eight bits define the direction of the
GPIO7..0 pins, respectively. A ‘1’ defines the
corresponding pin as an input, a ‘0’ as an
output.
Default value is 0xFF (all inputs).
Address Offset: 0x02C
Bit
Type
Mod
Description
31:24
RW
all
GenPurIO
- General Purpose Input/Output.
The function of this register depends on the
setting of GenPurDir.
For each pin configured as input (default):
- reading this bit will return the current value
of the input pin.
- writing to an input has no meaning, no
change of that bit.
For each pin configured as output:
- reading this bit will return the value on the
corresponding output pin. (If there is no
external short circuit, this is the last value
written by the host.)
- writing will change the output to the value
specified.
Default value is 0xF0.
23:16
R
Reserved. Returns zero.
15:14
RW
res
Duration time for guest 3:
00b - Tdur3 = 3 PCI clocks (default value),
01b - Tdur3 = 4 PCI clocks,
10b - Tdur3 = 12 PCI clocks,
11b - Tdur3 = 15 PCI clocks.
13:12
RW
res
Recovery time for guest 3:
00b - Trec3 = 3 PCI clocks (default value),
01b - Trec3 = 4 PCI clocks,
10b - Trec3 = 12 PCI clocks,
11b - Trec3 = 15 PCI clocks.
11:8
RW
res
Duration and recovery times for guest 2
(same structure as defined for guest 3
above).
7:4
RW
res
Duration and recovery times for guest 1
(same structure as defined for guest 3
above).
3:0
RW
res
Duration and recovery times for guest 0
(same structure as defined for guest 3
above).
Address Offset: 0x030
Bit
Type
Mod
Description
31:2
1:0
RW
R
cod
CodMemBase
- MPEG Code Memory Base
Address. This is the source starting address
for the code-read DMA transfers.
Default value is 0xFFFFFFFC.
Bits 1..0 are hardwired to 00b.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZR36067PQC | AV PCI CONTROLLER |
| ZR36067 | PCI Adapter Intended for Multimedia Applications on PCI Systems(PCI（外圍部件互連）適配器（用于PCI系統(tǒng)的多媒體）) |
| ZR36215 | SupraAV SVCD Decoder(SupraAV 超級VCD解碼器) |
| ZR36419 | Digital Camera Processor(數(shù)字?jǐn)z影處理器) |
| ZR36420 | Digital Camera Processor(數(shù)字?jǐn)z影處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZR36067PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
| ZR36067PQC-LV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| ZR36100PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Audio/Video Decoder for MPEG |
| ZR36110PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Audio/Video Decoder for MPEG |
| ZR36120PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。