參數(shù)資料
型號: ZPSD813F1V
英文描述: Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位閃速存儲器,256K位EEPROM,16K位SRAM)
中文描述: Flash在系統(tǒng)可編程Mirocomputer外設(閃速,在系統(tǒng)可編程微控制器外圍器件,100萬位閃速存儲器,256K位的EEPROM,16K的位的SRAM)
文件頁數(shù): 95/130頁
文件大小: 650K
代理商: ZPSD813F1V
Preliminary
PSD813F Family
91
-90
-12
-15
Symbol
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
t
LVLX
t
AVLX
t
LXAX
ALE or AS Pulse Width
20
22
28
Address Setup Time
(Note 1)
6
8
10
ns
Address Hold Time
(Note 1)
8
9
11
ns
t
AVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
20
25
30
ns
t
SLWL
t
DVWH
t
WHDX
t
WLWH
CS Valid to Leading Edge of WR
(Note 3)
25
30
35
ns
WR Data Setup Time
(Note 3)
35
40
45
ns
WR Data Hold Time
(Note 3)
5
5
5
ns
WR Pulse Width
(Note 3)
35
40
45
ns
t
WHAX
Trailing Edge of WR to Address
Invalid
(Note 3)
0
0
0
ns
t
WHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
30
35
38
ns
t
WLMV
WR Valid to Port Output Valid Using
Micro
Cell Register Preset/Clear
(Notes 3 and 4)
55
60
65
ns
Also including
pre-programming
time
t
WHQV1
Byte Programming Operation
14
14
14
μs
t
WHQV2
Sector Erase Operation
Note 100% tested
2.2
2.2
2.2
sec
t
Q7VQV
Q7 Valid to Output Valid
(Data Polling)
60
65
70
ns
t
VCS
V
CC
Setup Time
V
CC
High to First Flash WR Low
Data Valid to Port Output Valid
Using Micro
Cell Register
Preset/Clear
45
48
50
μs
t
DVMV
(Notes 3 and 5)
55
60
65
t
AVPV
Address Input Valid to Address
Output Delay
(Note 2)
32
40
48
ns
Write, Erase and Program Timing
(5 V ± 10% Versions)
NOTES:
1.
Any input used to select an internal PSD813F function.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
Assuming data is stable before active write signal.
Assuming write is active before data becomes valid.
2.
3.
4.
5.
Microcontroller Interface – PSD813F AC/DC Parameters
(5V ±10% Versions)
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