參數(shù)資料
型號(hào)： ZPSD502B1-12LI
英文描述： Field-Programmable Peripheral
中文描述： 現(xiàn)場(chǎng)可編程外圍
文件頁數(shù)： 46/153頁
文件大?。?/td> 1036K
代理商： ZPSD502B1-12LI
PSD5XX Famly
43
Control Register
This register is used in both Standard MCU I/O Mode and Address Out modes. For setting
a Standard MCU I/O Mode, a “1” must be written to the corresponding bit in the register.
Writing a “0” to the register is required for the Address Out mode. The register has a default
value of “0” after reset.
Drection Register
This register is used to control the direction of data flow in the I/O ports. Writing a “1” to
the corresponding bit in the register configures the port to be an output port, and a “0”
forces the port to be an input port. The I/O configuration of the port pins can be determined
by reading the Direction Register. After reset, the pins are in input mode.
Open Drain Register
This register determines whether the output pin driver of Port C or D is a CMOS driver or
an Open Drain driver. Writing a “0” to the register selects a CMOS driver, while a “1” selects
an Open Drain driver.
Special Function Register
Writing a “1” bit to this register sets up the corresponding pin to operate in Special Function
Out mode.
PLD– I/ORegister
This is a read only status register. Reading a "1" indicates the corresponding pin is
configured as a PLD pin. A "0" indicates the pin is an I/O pin.
Data In Register
This register is used in the Standard MCU I/O Mode configuration to read the input pins.
Data Out Register
This register holds the output data in the Standard MCU I/O Mode. The contents of the
register can also be read.
Macrocell Out Register
This register enables the user to read the outputs of the GPLD macrocell (PA, PB, and PE
macrocells).
I/ORegister Address Ofset
The I/O Register can be accessed by the microcontroller during normal read/write bus
cycles. The address of a register is defined as:
CSIOP + register address offset
The CSIOP is the base address that is defined in the ABEL file and occupies a 256 byte
space. The register address offset lies within this 256 byte space. Tables 15 and 15a are
the address offset of the registers.
I/OPorts
(Cont.)
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