參數(shù)資料
型號(hào)： ZL50031QEG1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PQFP256
封裝： 28 X 28 MM, 3.37 MM HEIGHT, LEAD FREE, MS-029, MQFP-256
文件頁數(shù)： 70/74頁
文件大小： 765K
代理商： ZL50031QEG1
ZL50031
Data Sheet
70
Zarlink Semiconductor Inc.
Figure 36 - Output Driver Enable (ODE)
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
*Note 1: A delay of 100 microseconds must be applied before the first microprocessor access is performed after the RESET pin is set high.
*Note 2: High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel the time taken to discharge C
L
.
AC Electrical Characteristics
- Motorola Non-Multiplexed Bus Mode
Characteristics
Sym.
Min.
Typ.
Max
Units
Test Conditions
1
1
CS setup from DS falling
t
CSS
t
RWS
t
ADS
t
CSH
t
RWH
t
ADH
t
DDR
t
DHR
0
ns
2
R/W setup from DS falling
15
ns
3
Address setup from DS falling
5
ns
4
CS hold after DS rising
0
ns
5
R/W hold after DS rising
0
ns
6
Address hold after DS rising
5
ns
7
Data setup from DTA Low on Read
20
ns
C
L
=30 pF
8
Data hold on read
20
ns
C
L
=30 pF, R
L
=1 K
See Note 2
9
Valid Write Data Setup
t
WDS
t
DHW
t
AKD
20
ns
10
Data hold on write
Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory
8
ns
11
97/82
158/114
110/95
171/127
30
ns
ns
C
L
=30 pF
C
L
=30 pF
C
L
=30 pF, R
L
=1 K,
See Note 2
12
Acknowledgment Hold Time
t
AKH
ns
V
TT
HiZ
HiZ
LSTo/BSTio
(Output)
ODE
t
ZD_ODE
Valid Data
V
TT
t
DZ_ODE
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