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參數(shù)資料
| 型號(hào)： | ZL50031QEG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQFP256 |
| 封裝： | 28 X 28 MM, 3.37 MM HEIGHT, LEAD FREE, MS-029, MQFP-256 |
| 文件頁(yè)數(shù)： | 35/74頁(yè) |
| 文件大小： | 765K |
| 代理商： | ZL50031QEG1 |
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ZL50031
Data Sheet
35
Zarlink Semiconductor Inc.
21.0 Register Descriptions
Bit
Name
Description
15-14
Unused
Reserved.
13-12
STS3-2
ST-BUS Frame Pulse and Clock Output Selection 1:
These two bits are used to select
different frequencies for the ST-BUS output frame pulse (ST_FPo1) and clock
(ST_CKo1).
11-10
STS1-0
ST-BUS Frame Pulse and Clock Output Selection 0:
These two bits are used to select
different frequencies for the ST-BUS output frame pulse (ST_FPo0) and clock
(ST_CKo0).
9
PRST
PRBS Reset:
When high, the PRBS transmitter output will be initialized.
8
CBERB
Backplane Bit Error Rate Test Clear:
A low to high transition of this bit will reset the
backplane internal bit error counter and the Backplane BER register (BBERR).
7
SBERB
Backplane Start Bit Error Rate Test:
A low to high transition in this bit starts the
backplane bit error rate test. The bit error test result is kept in the Backplane BER register
(BBERR).
6
CBERL
Local Bit Error Rate Test Clear:
A low to high transition of this bit will reset the local
internal bit error counter and the Local BER register (LBERR).
5
SBERL
Local Start Bit Error Rate Test:
A low to high transition in this bit starts the local bit error
rate test. The bit error test result is kept in the Local BER register (LBERR).
4
Unused
Reserved.
In normal functional mode, this bit
MUST
be set to zero.
3
MBP
Memory Block Programming:
When this bit is high, the connection memory block
programming feature is ready for the programming of bit 13 to bit 15 of the backplane
connection memory and local connection memory. When it is low this feature is disabled.
Table 8 - Control Register (CR) Bits
Read/Write Address: 0000
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
STS3
STS2
STS1
STS0
PRST
CBEBB
SBERB
CBERL
SBERL
0
MBP
MS2
MS1
MS0
STS3
0
0
1
STS2 ST_FPo1 Pulse Width
0
1
0
ST_CKo1 Frequency
4.096 MHz
8.192 MHz
16.384 MHz
244 ns
122 ns
61 ns
STS1
0
0
1
STS0 ST_FPo0 Pulse Width
0
1
0
ST_CKo0 Frequency
4.096 MHz
8.192 MHz
16.384 MHz
244 ns
122 ns
61 ns
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