參數(shù)資料
型號(hào): ZL50023GAC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 4 K Digital Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA256
封裝: 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256
文件頁數(shù): 59/80頁
文件大小: 1341K
代理商: ZL50023GAC
ZL50023
Data Sheet
59
Zarlink Semiconductor Inc.
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc-
tion testing.
Figure 20 - Motorola Non-Multiplexed Bus Timing - Read Access
AC Electrical Characteristics
- Motorola Non-Multiplexed Bus Mode - Read Access
Characteristics
Sym
Min.
Typ.
Max.
Units
Test Conditions
2
1
2
3
4
5
6
7
8
9
CS de-asserted time
DS de-asserted time
CS setup to DS falling
R/W setup to DS falling
Address setup to DS falling
CS hold after DS rising
R/W hold after DS rising
Address hold after DS rising
Data setup to DTA Low
10 Data hold after DS rising
t
CSD
t
DSD
t
CSS
t
RWS
t
AS
t
CSH
t
RWH
t
AH
t
DS
t
DHZ
15
15
0
10
5
0
0
0
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
L
= 50 pF
C
L
= 50 pF, R
L
= 1 K
(Note 1)
8
11 Acknowledgement delay time.
From DS low to DTA low:
Registers
Memory
t
AKD
75
185
12
ns
ns
ns
C
L
= 50 pF
C
L
= 50 pF
12 Acknowledgement hold time.
From DS high to DTA high
13 DTA drive high to HiZ
t
AKH
4
C
L
= 50 pF, R
L
= 1 K
(Note 1)
t
AKZ
8
ns
Note 1:
High impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to
discharge C
L
.
A delay of 500
μ
s to 2 ms (see Section 14.2 on page 31) must be applied before the first microprocessor access is
performed after the RESET pin is set high.
Note 2:
DS
A0-A13
D0-D15
t
CSH
t
AH
t
RWS
R/W
t
AS
t
RWH
t
AKD
t
DS
t
AKH
DTA
V
CT
V
CT
V
CT
V
CT
V
CT
V
CT
VALID ADDRESS
VALID READ DATA
t
CSS
t
DSD
CS
t
AKZ
t
CSD
t
DHZ
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