參數(shù)資料
型號: ZL50023GAC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 4 K Digital Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA256
封裝: 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256
文件頁數(shù): 38/80頁
文件大?。?/td> 1341K
代理商: ZL50023GAC
ZL50023
Data Sheet
38
Zarlink Semiconductor Inc.
Bit
Name
Description
15 - 9
Unused
Reserved.
In normal functional mode, these bits
MUST
be set to zero.
8
STIO_PD_
EN
STio Pull-down Enable
When this bit is low, the pull-down resistors on all STio pads will be disabled.
When this bit is high, the pull-down resistors on all STio pads will be enabled.
7
BDH
Bi-directional Control for Streams 16-31
6
BDL
Bi-directional Control for Streams 0-15
5
RBEREN
PRBS Receiver Enable
When this bit is low, all the BER receivers are disabled. To enable any BER receivers,
this bit
MUST
be high.
4
TBEREN
PRBS Transmitter Enable
When this bit is low, all the BER transmitters are disabled. To enable any BER
transmitters, this bit
MUST
be high.
3 - 1
BPD2 - 0
Block Programming Data
These bits refer to the value to be loaded into the connection memory, whenever the
memory block programming feature is activated. After the MBPE bit in the Control
Register is set to high and the MBPS bit in this register is set to high, the contents of
the bits BPD2 - 0 are loaded into bits 2 - 0 of the Connection Memory Low. Bits 15 - 3
of the Connection Memory Low and bits 15 - 0 of Connection Memory High are
zeroed.
Table 15 - Internal Mode Selection Register (IMS) Bits
External Read/Write Address: 0001
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
STIO_
PD_EN
BDH
BDL
RBER
EN
TBER
EN
BPD
2
BPD
1
BPD
0
MBPS
BDH
STio16 - 31 Operation
0
normal operation:
STi16-31 are inputs
STio16-31 are outputs
1
bi-directional operation:
STi16-31 tied low internally
STio16-31 are bi-directional
BDL
STio0 - 15 Operation
0
normal operation:
STi0-15 are inputs
STio0-15 are outputs
1
bi-directional operation:
STi0-15 tied low internally
STio0-15 are bi-directional
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