參數(shù)資料
型號(hào): ZL30122GGG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: SONET/SDH Low Jitter Line Card Synchronizer
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PBGA64
封裝: 9 X 9 MM, 1 MM PITCH, CABGA-64
文件頁(yè)數(shù): 16/23頁(yè)
文件大?。?/td> 246K
代理商: ZL30122GGG
ZL30122
Data Sheet
16
Zarlink Semiconductor Inc.
2.0 Software Configuration
The ZL30122 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The
device can be configured to operate in a highly automated manner which minimizes its interaction with the system’s
processor, or it can operate in a manual mode where the system processor controls most of the operation of the
device.
The following table provides a summary of the registers available for status updates and configuration of the device.
.
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description
Type
Miscellaneous Registers
00
id_reg
A6
Chip and version identification and reset ready
indication register
R
01
use_hw_ctrl
00
Allows some functions of the device to be
controlled by hardware pins
R/W
Interrupts
02
ref_fail_isr
FF
Reference failure interrupt service register
R
03
dpll_isr
70
DPLL interrupt service register
StickR
04
Reserved
Leave as default
05
ref_mon_fail_0
FF
Ref0 and ref1 failure indications
StickR
06
ref_mon_fail_1
FF
Ref2 failure indication.
StickR
07
Reserved
Leave as default
08
Reserved
Leave as default
09
ref_fail_isr_mask
00
Reference failure interrupt service register
mask
R/W
0A
dpll_isr_mask
00
DPLL interrupt service register mask
R/W
0B
Reserved
Leave as default
0C
ref_mon_fail_mask_0
FF
Control register to mask each failure indicator
for ref0 and ref1
R/W
0D
ref_mon_fail_mask_1
FF
Control register to mask failure indicator for
ref2
R/W
0E
Reserved
Leave as default
0F
Reserved
Leave as default
Reference Monitor Setup
10
detected_ref_0
FF
Ref0 and ref1 auto-detected frequency value
status register
R
11
detected_ref_1
FF
Ref2 auto-detected frequency value status
register
R
12
Reserved
Leave as default
R
13
Reserved
Leave as default
R
Table 5 - Register Map
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