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參數(shù)資料
| 型號： | ZL30120GGG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA100 |
| 封裝： | 9 X 9 MM, 0.80 MM PITCH, CABGA-100 |
| 文件頁數(shù)： | 14/27頁 |
| 文件大?。?/td> | 309K |
| 代理商： | ZL30120GGG |
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ZL30120
Data Sheet
14
Zarlink Semiconductor Inc.
Each of the
ref
inputs accept a single-ended LVCMOS clock with a frequency ranging from 2 kHz to 77.76 MHz.
Built-in frequency detection circuitry automatically determines the frequency of the reference if its frequency is
within the set of pre-defined frequencies as shown in Table 2. Custom frequencies definable in multiples of 8 kHz
are also available.
Each of the
sync
inputs accept a single-ended LVCMOS frame pulse. Since alignment is determined from the rising
edge of the frame pulse, there is no duty cycle restriction on this input, but there is a minimum pulse width
requirement of 5 ns. Frequency detection for the sync inputs is automatic for the supported frame pulse frequencies
shown in Table 3.
1.4 Ref and Sync Monitoring
All input references (
ref0
to
ref7
) are monitored for frequency accuracy and phase regularity. New references are
qualified before they can be selected as a synchronization source, and qualified references are continuously
monitored to ensure that they are suitable for synchronization. The process of qualifying a reference depends on
four levels of monitoring.
Single Cycle Monitor (SCM)
The SCM block measures the period of each reference clock cycle to detect phase irregularities or a missing clock
edge. In general, if the measured period deviates by more than 50% from the nominal period, then an SCM failure
(scm_fail) is declared.
2 kHz
8 kHz
64 kHz
1.544 MHz
2.048 MHz
6.48 MHz
8.192 MHz
16.384 MHz
19.44 MHz
38.88 MHz
77.76 MHz
Custom A
Custom B
Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies
166.67 Hz
(48x 125
μ
s frames)
400 Hz
1 kHz
2 kHz
8 kHz
64 kHz
Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30120GGG2 | SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer |
| ZL30121GGG2 | SONET/SDH Low Jitter System Synchronizer |
| ZL30121 | SONET/SDH Low Jitter System Synchronizer |
| ZL30121GGG | SONET/SDH Low Jitter System Synchronizer |
| ZL30122 | SONET/SDH Low Jitter Line Card Synchronizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30120GGG2 | 制造商:Microsemi Corporation 功能描述:LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC LINE CARD SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC LINE CARD SYNCH 100CABGA |
| ZL30121 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Low Jitter System Synchronizer |
| ZL30121GGG | 制造商:Microsemi Corporation 功能描述:SYS SYNCHRONIZER 100CABGA - Trays |
| ZL30121GGG2 | 制造商:Microsemi Corporation 功能描述:PB FREE LOW JITTER SYSTEM SYNCHRONIZER |
| ZL30121GGG2V2 | 制造商:Microsemi Corporation 功能描述:REV 2 PB FREE LOW JITTER SYSTEM SYNCHRO 制造商:Microsemi Corporation 功能描述:REV 2 PB FREE LOW JITTER SYSTEM SYNCHRO - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA |
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