參數(shù)資料
型號(hào)： ZL30120
廠商： Zarlink Semiconductor Inc.
英文描述： SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
中文描述： 的SONET / SDH /以太網(wǎng)多速率線路卡同步器
文件頁(yè)數(shù)： 12/27頁(yè)
文件大?。?/td> 309K
代理商： ZL30120
ZL30120
Data Sheet
12
Zarlink Semiconductor Inc.
1.2 DPLL Mode Control
Both DPLL1 and DPLL2 independently support three modes of operation - free-run, normal and holdover. The
mode of operation can be manually set or controlled by an automatic state machine as shown in Figure 2.
Figure 2 - Automatic Mode State Machine
Free-run
The free-run mode occurs immediately after a reset cycle or when the DPLL has never been synchronized to a
reference input. In this mode, the frequency accuracy of the output clocks is equal to the frequency accuracy of the
external master oscillator.
Lock Acquisition
The input references are continuously monitored for frequency accuracy and phase regularity. If at least one of the
input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given
a stable reference input, the ZL30120 will enter in the Normal (locked) mode.
Normal (locked)
The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified
reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency
accuracy of the reference input. While in the normal mode, the DPLL’s clock and frame pulse outputs comply with
the MTIE and TDEV wander generation specifications as described in Telcordia and ITU-T telecommunication
standards.
Holdover
When the DPLL operating in the normal mode loses its reference input, and no other qualified references are
available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data
collected while the DPLL was synchronized.
Reset
Another reference is
qualified and available
for selection
Phase lock on
the selected
reference is
achieved
Lock
Acquisition
(Locked)
No references are
qualified and
available for
selection
Free-Run
Holdover
Selected reference
fails
All references are monitored
for frequency accuracy and
phase regularity, and at least
one reference is qualified.
Normal
相關(guān)PDF資料
PDF描述
ZL30120GGG SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
ZL30120GGG2 SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
ZL30121GGG2 SONET/SDH Low Jitter System Synchronizer
ZL30121 SONET/SDH Low Jitter System Synchronizer
ZL30121GGG SONET/SDH Low Jitter System Synchronizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL30120GGG 制造商:Microsemi Corporation 功能描述:T1/E1 SYSTEM SYNCHRONIZER 制造商:Microsemi Corporation 功能描述:LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC LINE CARD SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC LINE CARD SYNCH 100CABGA
ZL30120GGG2 制造商:Microsemi Corporation 功能描述:LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC LINE CARD SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC LINE CARD SYNCH 100CABGA
ZL30121 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Low Jitter System Synchronizer
ZL30121GGG 制造商:Microsemi Corporation 功能描述:SYS SYNCHRONIZER 100CABGA - Trays
ZL30121GGG2 制造商:Microsemi Corporation 功能描述:PB FREE LOW JITTER SYSTEM SYNCHRONIZER
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