參數(shù)資料
型號(hào)： ZL30117GGG2
廠商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： SONET/SDH OC-48/OC-192 Line Card Synchronizer
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA64
封裝： 9 X 9 MM, 1 MM PITCH, LEAD FREE, CABGA-64
文件頁(yè)數(shù)： 11/24頁(yè)
文件大?。?/td> 388K
代理商： ZL30117GGG2
ZL30117
Data Sheet
11
Zarlink Semiconductor Inc.
1.2 DPLL Mode Of Operation
The DPLL supports three modes of operation - free-run, normal, and holdover. The mode of operation can be
manually set or controlled by an automatic state machine as shown in Figure 2.
Figure 2 - Automatic Mode State Machine
Free-run
The free-run mode occurs immediately after a reset cycle or when the DPLL has never been synchronized to a
reference input. In this mode, the frequency accuracy of the output clocks is equal to the frequency accuracy of the
external master oscillator.
Lock Acquisition
The input references are continuously monitored for frequency accuracy and phase regularity. If at least one of the
input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given
a stable reference input, the ZL30117 will enter in the Normal (locked) mode.
Normal (locked)
The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified
reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency
accuracy of the reference input. While in the normal mode, the DPLL’s clock and frame pulse outputs comply with
the MTIE and TDEV wander generation specifications as described in Telcordia and ITU-T telecommunication
standards.
Holdover
When the DPLL operating in the normal mode loses its reference input, and no other qualified references are
available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data
collected while the DPLL was synchronized. The transition between normal and holdover modes is controlled by
the DPLL so that its initial frequency offset is better than 100 ppb. The frequency drift after this transition period is
dependant on the frequency drift of the external master oscillator.
Reset
Another reference is
qualified and available
for selection
Phase lock on
the selected
reference is
achieved
Lock
Acquisition
(Locked)
No references are
qualified and
available for
selection
Free-Run
Holdover
Selected reference
fails
All references are monitored
for frequency accuracy and
phase regularity, and at least
one reference is qualified.
Normal
相關(guān)PDF資料
PDF描述
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ZL30119_06 SONET/SDH OC-48/OC-192 Line Card Synchronizer
ZL30119GGG SONET/SDH OC-48/OC-192 Line Card Synchronizer
ZL30119GGG2 SONET/SDH OC-48/OC-192 Line Card Synchronizer
ZL30120 SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL30119 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:SONET/SDH OC-48/OC-192 Line Card Synchronizer
ZL30119_06 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:SONET/SDH OC-48/OC-192 Line Card Synchronizer
ZL30119GGG 制造商:Microsemi Corporation 功能描述:LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:Microsemi Corporation 功能描述:LOW JITTER LINECARD SYNCHRONIZER 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA
ZL30119GGG2 制造商:Microsemi Corporation 功能描述:LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA
ZL30120 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
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