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參數(shù)資料
| 型號： | ZL30108LDA |
| 廠商： | XILINX INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, MO-220, QFN-32 |
| 文件頁數(shù)： | 36/57頁 |
| 文件大?。?/td> | 691K |
| 代理商： | ZL30108LDA |
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ZL30108
Data Sheet
14
Zarlink Semiconductor Inc.
5.0
Control and Modes of Operation
5.1
Out of Range Selection
The frequency out of range limits for the precise frequency monitoring in the reference monitors are selected by the
OOR_SEL pin, see Table 2.
5.2
Modes of Operation
The ZL30108 has two possible manual modes of operation; Normal and Freerun. These modes are selected with
mode select pins MODE_SEL as is shown in Table 3. Transitioning from one mode to the other is controlled
externally.
5.2.1
Freerun Mode
Freerun mode is typically used when an independent clock source is required, or immediately following system
power-up before network synchronization is achieved.
In Freerun mode, the ZL30108 provides timing and synchronization signals which are based on the master clock
frequency (supplied to OSCi pin) only, and are not synchronized to the reference input signals.
The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a
±32 ppm output clock
is required, the master clock must also be
±32 ppm. See Applications - Section 7.2, “Master Clock“.
5.2.2
Normal Mode
Normal mode is typically used when a system clock source, synchronized to the network or a backplane is required.
In Normal mode, the ZL30108 provides timing and frame synchronization signals, which are synchronized to one of
two reference inputs (REF0 or REF1). The input reference signal may have a nominal frequency of 2 kHz, 8 kHz,
1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. The frequency of the reference inputs are
automatically detected by the reference monitors.
When the Normal mode is selected through the MODE_SEL pin, the ZL30108 will automatically go into the
Automatic Holdover mode if the currently selected reference is disrupted (see Figure 9). After the power up reset,
the ZL30108 will initially go into the Automatic Holdover mode, generating clocks with the same accuracy as it
would be in the Freerun mode. If the currently selected reference is not disrupted (see Figure 3), the state machine
takes the DPLL out of the Automatic Holdover mode. The transition is done through the TIE correction state and the
current phase offset of the output signals to the input reference is maintained.
OOR_SEL
Out Of Range Limits
0
40 - 52 ppm
1
64 - 83 ppm
Table 2 - Out of Range Limits Selection
MODE_SEL
Mode
0
Normal (with automatic Holdover)
1
Freerun
Table 3 - Operating Modes
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30108LDE1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Network Interface DPLL |
| ZL30108LDG1 | 制造商:Microsemi Corporation 功能描述:PB FREE SONET/SDH NETWORK INTERFACE DPLL - Trays 制造商:Microsemi Corporation 功能描述:PBFREE SONET&SDH NETWORK I/F DPLL TRAY 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DPLL SONET/SDH 32QFN 制造商:Microsemi Corporation 功能描述:IC DPLL SONET/SDH 32QFN |
| ZL30109 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:DS1/E1 System Synchronizer with 19.44 MHz Output |
| ZL30109_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:DS1/E1 System Synchronizer with |
| ZL30109QDG | 制造商:Microsemi Corporation 功能描述: |
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