參數(shù)資料
型號(hào)： ZL30316GKG2
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, MO-034B, TEBGA-256
文件頁(yè)數(shù)： 1/5頁(yè)
文件大?。?/td> 112K
代理商： ZL30316GKG2
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.
A full Design Manual is available to qualified customers.
To register, please send an email to
TimingandSync@Zarlink.com.
Features
Recovers and transmits network synchronization
over Ethernet, IP and MPLS Networks
Simultaneously supports both the Synchronous
Ethernet and the IEEE1588 industry standard timing
protocols
Capable of server, client and repeater operation
Integrates two separate digital phase locked loops,
with hitless switching between packet and electrical
clock references
Targeted for synchronization distribution to better
than ITU-T G.8261, G.823, G.824 and ANSI T1.101
synchronization interface standards
Average frequency accuracy better than ±10 ppb
Aligns to a low frequency input signal at server
(e.g., 1 Hz) with targeted accuracy better than ±1
μs
Recovers clocks from two independent servers, with
hitless switching between packet streams for
redundancy
Supports holdover if the server stream is lost
Accepts eight input references, and up to three
associated low frequency alignment or framing pulses
Generates up to four separate output clocks at
frequencies between 8 kHz and 100 MHz
Generates two separate Synchronous Ethernet
clocks to drive industry standard Ethernet PHY
devices at either 25 MHz or 125 MHz
Fully configurable solution, enabling performance
to be tailored to application/network requirements
Two independently configurable MAC interfaces,
supporting MII, RMII, GMII and TBI standards
Wire-speed Ethernet Bridge pass through function
between the MAC interfaces
Synchronous serial control interface
Full demonstration & evaluation platform available
Applications
IEEE 1588 and Synchronous Ethernet timing
GSM and UMTS air interface synchronization
over a packet network
Circuit Emulation Services over Packets
IP-PBX and VoIP Gateways
Video Conferencing
Broadband Video Distribution
June 2009
Ordering Information
ZL30316GKG
256 TEPBGA, 17 x 17 mm
ZL30316GKG2
256 TEPBGA, 17 x 17 mm
-40°C to +85°C
ZL30316
Combined Synchronous Ethernet and
IEEE1588 Timing over Packet Technology
Data Sheet
Figure 1 - ZL30316 Functional Block Diagram
ToP
PLL
MAC
Port M2
Network I/F
(GMII/TBI/MII/RMII)
Port M1
Processor I/F
(GMII/TBI/MII/RMII)
SSI
Ethernet Bridge
Timestamp Engine
Register
Access I/F
p1_clk1
p1_clk0
p0_clk0
p0_clk1
p0_fp0
p0_fp1
Input Ports
&
Ref
Monitors
DPLL 1
Stratum 3
ETH_CLK0
ETH_CLK1
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
sync0
sync1
sync2
DPLL2
P0
Synthesizer
P1
Synthesizer
APLL
refn
refm
syncn
osci
osco
Master
Osc
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