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參數(shù)資料
| 型號： | ZL30106QDG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/PDH Network Interface DPLL |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.0 MM HEIGHT, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 11/48頁 |
| 文件大?。?/td> | 423K |
| 代理商： | ZL30106QDG |
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ZL30106
Data Sheet
11
Zarlink Semiconductor Inc.
55
REF0
Reference (Input).
This is one of three (REF0, REF1 and REF2) input reference sources
used for synchronization. One of seven possible frequencies may be used: 2 kHz, 8 kHz,
1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. This pin is internally
pulled down to GND.
56
REF_SYNC0
REF Synchronization Frame Pulse 0 (Input).
This is the 2 kHz or 8 kHz (multi) frame
pulse synchronization input associated with the REF0 reference. While the PLL is locked
to the REF0 input reference the output (multi) frame pulses are synchronized to this
input. This pin is internally pulled down to GND.
57
REF1
Reference (Input).
See REF0 pin description.
58
REF_SYNC1
REF Synchronization Frame Pulse 1 (Input).
This is the 2 kHz or 8 kHz (multi) frame
pulse synchronization input associated with the REF1 reference. While the PLL is locked
to the REF1 input reference the output (multi) frame pulses are synchronized to this
input. This pin is internally pulled down to GND.
59
REF2
Reference (Input).
See REF0 pin description.
60
APP_SEL0
Application Selection (Input).
See APP_SEL1 pin description.
61
V
DD
NC
Positive Supply Voltage.
+3.3 V
DC
nominal
No internal bonding Connection.
Leave unconnected.
62
63
TIE_CLR
TIE Circuit Reset (Input).
A logic low at this input resets the Time Interval Error (TIE)
correction circuit resulting in a realignment of input phase with output phase.
64
BW_SEL
Filter Bandwidth Selection (Input).
This pin selects the bandwidth of the DPLL loop
filter, see Table 2 on page 20.
Pin #
Name
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30107 | GbE Line Card Synchronizer |
| ZL30107GGG | GbE Line Card Synchronizer |
| ZL30107GGG2 | GbE Line Card Synchronizer |
| ZL30108LDA | Network Interface DPLL |
| ZL30108 | Network Interface DPLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30106QDG1 | 制造商:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH NETWORK INTRFC 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE SONET/SDH/PDH NTWK INTERFACEDPLL |
| ZL30107 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:GbE Line Card Synchronizer |
| ZL30107GGG | 制造商:Microsemi Corporation 功能描述: 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER ETH SGL 64CABGA 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER ETH SGL 64CABGA |
| ZL30107GGG2 | 制造商:Microsemi Corporation 功能描述:GBE LINE CARD SYNCHRONIZER 64CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER ETH SGL 64CABGA 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER ETH SGL 64CABGA |
| ZL30108 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Network Interface DPLL |
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