參數(shù)資料
型號： ZL30106
廠商： Zarlink Semiconductor Inc.
英文描述： SONET/SDH/PDH Network Interface DPLL
中文描述： 的SONET / SDH / PDH數(shù)字網(wǎng)絡(luò)接口全數(shù)字鎖相環(huán)
文件頁數(shù)： 9/48頁
文件大?。?/td> 423K
代理商： ZL30106
ZL30106
Data Sheet
9
Zarlink Semiconductor Inc.
19
RST
Reset (Input).
A logic low at this input resets the device. On power up, the RST pin
must be held low for a minimum of 300 ns after the power supply pins have reached
the minimum supply voltage. When the RST pin goes high, the device will transition
into a Reset state for 3 ms. In the Reset state all outputs will be forced into high
impedance.
20
OSCo
Oscillator Master Clock (Output).
For crystal operation, a 20 MHz crystal is connected
from this pin to OSCi. This output is not suitable for driving other devices. For clock
oscillator operation, this pin must be left unconnected.
21
OSCi
Oscillator Master Clock (Input).
For crystal operation, a 20 MHz crystal is connected
from this pin to OSCo. For clock oscillator operation, this pin must be connected to a
clock source.
22
IC
Internal Connection.
Leave unconnected.
23
GND
Ground.
0 V
24
APP_SEL1
Application Selection 1 (Input).
This input combined with APP_SEL0 selects the
application that the ZL30106 is optimized for, see Table 1 on page 20.
25
V
DD
Positive Supply Voltage.
+3.3 V
DC
nominal
Output Selection 2 (Input).
This input selects the signals on the combined output clock
and frame pulse pins, see Table 3 on page 21.
26
OUT_SEL2
27
OUT_SEL1
Output Selection 1 (Input).
This input combined with OUT_SEL0 selects the signals on
the combined output clock pin C6/8.4/34/44o, see Table 3 on page 21.
28
OUT_SEL0
Output Selection 0 (Input).
See OUT_SEL1 description.
29
AV
DD
Positive Analog Supply Voltage.
+3.3 V
DC
nominal
C6/8.4/34/44o
Clock 6.312 MHz, 8.448 MHz, 34.368 MHz or 44.736 MHz (Output).
This output is used
in DS2, E2, E3 or DS3 applications. The output frequency is selected via the OUT_SEL1
and OUT_SEL0 pins, see Table 3 on page 21.
30
31
C3o
Clock 3.088 MHz (Output).
This output is used in DS1 applications.
32
C1.5o
Clock 1.544 MHz (Output).
This output is used in DS1 applications.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
33
AGND
Analog Ground.
0 V
34
AGND
Analog Ground.
0 V
35
AV
CORE
AV
DD
AV
DD
F2ko
Positive Analog Supply Voltage.
+1.8 V
DC
nominal
Positive Analog Supply Voltage.
+3.3 V
DC
nominal
Positive Analog Supply Voltage.
+3.3 V
DC
nominal
Multi Frame Pulse (Output).
This is a 2 kHz 51 ns active high framing pulse, which
marks the beginning of a multi frame.
36
37
38
39
C19o
Clock 19.44 MHz (Output).
This output is used in SONET/SDH applications.
40
AGND
Analog Ground.
0 V
41
AGND
Analog Ground.
0 V
Pin #
Name
Description
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