參數(shù)資料
型號： ZL30106
廠商： Zarlink Semiconductor Inc.
英文描述： SONET/SDH/PDH Network Interface DPLL
中文描述： 的SONET / SDH / PDH數(shù)字網(wǎng)絡(luò)接口全數(shù)字鎖相環(huán)
文件頁數(shù)： 27/48頁
文件大?。?/td> 423K
代理商： ZL30106
ZL30106
Data Sheet
27
Zarlink Semiconductor Inc.
Figure 17 - Automatic Reference Switching - Out-of-Range Reference Failure
4.6 Clock-and-Sync Pair Synchronization
The ZL30106 can lock directly to a 2 kHz reference or an 8 kHz reference, but the low frequency of these
references restricts the value of the highest loop filter that can be used. The clock-and-sync pair synchronization
technique enables the ZL30106 to align its output 2 kHz and 8 kHz frame pulses with 2 kHz and 8 kHz references
without restricting the loop filter. Therefore the output clocks and frame pulses will track the input clock and frame
pulse pair closely even in the presence of jitter on the reference input.
The clock-and-sync pair mechanism is enabled as soon as a valid 2 kHz or 8 kHz frame pulse is detected on the
REF_SYNC input. The REF_SYNC pulse must be generated from the clock that is present on the REF input. The
ZL30106 checks the number of REF cycles in the REF_SYNC period. If this is not the nominal number of cycles,
the REF_SYNC pulse is considered invalid. For example, if REF is a 8.192 MHz clock then there must be exactly
1024 REF cycles in a REF_SYNC period. If a valid REF_SYNC pulse is detected, the ZL30106 will align the rising
edges of the REF clock and the corresponding output clock such that the rising edge of the F2ko or F8o/F32o
output frame pulse is aligned with the frame boundary indicated by the REF_SYNC signal. The rising edges of the
REF and the corresponding output clock that are aligned, are the ones that lag the rising edges of the REF_SYNC
and the F8o pulses respectively. This is illustrated in Figure 18. If an ST_BUS clock and frame pulse pair is used as
the REF and REF_SYNC inputs, the ST-BUS frame pulse must be inverted first before it can be used as the
REF_SYNC pulse.
If a clock and frame pulse pair is used for synchronization, the TIE correction value should be cleared by keeping
the TIE_CLR pin low for at least 15 ns. Otherwise a static phase offset may remain between the output frame pulse
and the REF_SYNC frame pulse. Reference switching from one REF- REF_SYNC pair to the other REF-
REF_SYNC pair does not activate the TIE correction circuit and the ZL30106 will align the output frame pulse to the
new REF_SYNC frame pulse. In that case the MTIE can be as large as 250
μ
s for a 2 kHz REF_SYNC signal and
10 to 20 s
REF0
REF_FAIL0
HOLDOVER
REF_OOR0
(internal signal)
REF1
REF0
REF_SEL
Frequency Precision failure
LOCK
Note: This scenario is based on REF1 remaining good throughout the duration.
LOCK pin behaviour depends on phase and frequency offset of REF1.
Lock Time
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL30106_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL
ZL30106QDG 制造商:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH NETWORK INTRFC 64TQFP - Trays 制造商:Microsemi 功能描述:Microsemi ZL30106QDG Communication Misc
ZL30106QDG1 制造商:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH NETWORK INTRFC 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE SONET/SDH/PDH NTWK INTERFACEDPLL
ZL30107 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:GbE Line Card Synchronizer
ZL30107GGG 制造商:Microsemi Corporation 功能描述: 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER ETH SGL 64CABGA 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER ETH SGL 64CABGA
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