- 您現(xiàn)在的位置：買賣IC網 > PDF目錄373782 > ZL10312QCG (ZARLINK SEMICONDUCTOR INC) Satellite Demodulator PDF資料下載
參數(shù)資料
| 型號： | ZL10312QCG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 消費家電 |
| 英文描述： | Satellite Demodulator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-64 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大小： | 340K |
| 代理商： | ZL10312QCG |
ZL10312
Data Sheet
6
Zarlink Semiconductor Inc.
1.0 Functional Overview
1.1 Introduction
ZL10312 is a single-chip variable rate digital QPSK/BPSK satellite demodulator and channel decoder. The
ZL10312 accepts base-band in-phase and quadrature analogue signals and delivers an MPEG or DSS packet data
stream. Digital filtering in ZL10312 removes the need for programmable external anti-alias filtering for all symbol
rates from 1 - 45 MSps. Frequency, timing and carrier phase recovery are all digital and the only feed-back to the
analogue front-end is for automatic gain control. The digital phase recovery loop enables very fine bandwidth
control that is needed to overcome performance degradation due to phase and thermal noise.
All acquisition algorithms are built into the ZL10312 controller. The ZL10312 can be operated in a Command Driven
Control (CDC) mode by specifying the symbol rate and Viterbi code rate. There is also a provision for a search for
unknown symbol rates and Viterbi code rates.
1.2 Analogue-to-Digital Converter and PLL
The A/D converters sample single-ended or differential analogue inputs and consist of a dual ADC and circuitry to
provide improved SiNaD (Signal-Noise and Distortion) and channel matching.
The fixed rate sampling clock is provided on-chip using a programmable PLL needing only a low cost 10 to 16 MHz
crystal. Different crystal frequencies can be combined with different PLL ratios, depending on the maximum symbol
rate, allowing a very flexible approach to clock generation. An external clock signal in the range 4 to 16 MHz can
also be used as the master clock.
1.3 QPSK Demodulator
The demodulator in the ZL10312 consists of signal amplitude offset compensation, frequency offset compensation,
decimation filtering, carrier recovery, symbol recovery and matched filtering. The decimation filters give continuous
operation from 2Mbits/s to 90Mbits/s allowing one receiver to cover the needs of the consumer market as well as
the single carrier per channel (SCPC) market with the same components without compromising performance, that
is, the channel reception is within 0.5dB of theoretical. For a given symbol rate, control algorithms on the chip
detect the number of decimation stages needed and switch them in automatically.
The frequency offset compensation circuitry is capable of tracking out up to ±22.5 MHz frequency offset. This
allows the system to cope with relatively large frequency uncertainties introduced by the Low Noise Block (LNB).
Full control of the LNB is provided by the DiSEqC outputs from the ZL10312. Horizontal/vertical polarisation and an
instruction modulated 22kHz signal are available under register control. All DiSEqC v2.x functions are implemented
on the ZL10312. An internal state machine that handles all the demodulator functions controls the signal acquisition
and tracking. Various pre-set modes are available as well as blind acquisition where the receiver has no prior
knowledge of the received signal. Fast acquisition algorithms have been provided for low symbol rate applications.
Full interactive control of the acquisition function is possible for debug purposes. In the event of a signal fade or a
cycle slip, the QPSK demodulator allows sufficient time for the FEC to re-acquire lock, for example, via a phase
rotation in the Viterbi decoder. This is to minimise the loss of signal due to the signal fade. Only if the FEC fails to
re-acquire lock for a long period (which is programmable) would QPSK try to re-acquire the signal.
The matched filter is a root-raised-cosine filter with either 0.20 or 0.35 roll-off, compliant with DSS and DVB
standards. Although not a part of the DVB standard, ZL10312 allows a roll-off of 0.20 to be used with other DVB
parameters. An AGC signal is provided to control the signal levels in the tuner section of the receiver and ensure
the signal level fed to the ZL10312 is set at an optimal value under all reception conditions.
The ZL10312 provides comprehensive information on the input signal and the state of the various parts of the
device. This information includes signal to noise ratio (SNR), signal level, AGC lock, timing and carrier lock signals.
A maskable interrupt output is available to inform the host controller when events occur.
相關PDF資料 |
PDF描述 |
|---|---|
| ZL10312QCG1 | Satellite Demodulator |
| ZL10312UBH | Satellite Demodulator |
| ZL10312 | Satellite Demodulator |
| ZL10313QCG | Augumented Cat. 6 T568A/B Modular Jack; No. of Ports:24; Mounting Type:1U Panel; Approval Categories:Augmented Category 6; Jacks FCC part 68, Subpart F & IEC-603-7 compliant RoHS Compliant: Yes |
| ZL10313QCG1 | Augumented Cat. 6 T568A/B Modular Jack; No. of Ports:48; Mounting Type:2U Panel; Approval Categories:Augmented Category 6; Jacks FCC part 68, Subpart F & IEC-603-7 compliant RoHS Compliant: Yes |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ZL10312QCG1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator |
| ZL10312UBH | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator |
| ZL10313 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator |
| ZL10313QCG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator |
| ZL10313QCG1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator |
發(fā)布緊急采購，3分鐘左右您將得到回復。