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參數(shù)資料
| 型號： | ZL10312QCG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 消費家電 |
| 英文描述： | Satellite Demodulator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-64 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 340K |
| 代理商： | ZL10312QCG |
ZL10312
Data Sheet
11
Zarlink Semiconductor Inc.
2.6 ZL10312 Pinout Description
Pin Description Table
Pin
Name
Description
I/O
Note
V
mA
1
Reset
Active low reset input
I
CMOS
1
5
2
DiSEqC[2]
DiSEqC input for level 2 control. Also usable as
GPP2 (general purpose port pin) for other purposes.
I/O
Open
drain
1
5
6
3
DiSEqC[1]
Horizontal/vertical LNB control (acts as input only in
production test modes)
I/O
CMOS
3.3
2
4
DiSEqC[0]
22 kHz output to LNB (acts as input only in
production test modes)
I/O
CMOS
3.3
2
9
Sleep
Stops oscillator and sets minimum power levels to
entire device (except ADCs - register controlled
power-down)
I
CMOS
3.3
10
CLK1
Primary 2-wire serial bus clock
I
CMOS
1
5
11
DATA1
Primary 2-wire serial bus data
I/O
Open
drain
1
5
6
14
DATA2
Secondary 2-wire bus data to tuner front end. Also
usable as GPP1 (general purpose port pin) for other
purposes.
I/O
Open
drain
1
5
6
15
CLK2
Secondary 2-wire bus clock to tuner front end. Also
usable as GPP0 (general purpose port pin) for other
purposes.
I/O
Open
drain
1
5
6
16
OscMode
Controls oscillator mode to suit crystal or external
signal
I
CMOS
3.3
19
XTI
Crystal input or external reference clock input
I
CMOS
1.8
20
XTO
Crystal output, includes internal feedback resistor to
XTI
I/O
CMOS
1.8
24
Iin
I channel input
I
analog
25
Iin
I channel negative input
I
analog
29
Qin
Q channel negative input
I
analog
30
Qin
Q channel input
I
analog
35,36,37
38
ADDR[1:4]
Primary 2-wire bus address defining pins
I
CMOS
3.3
41
AGC
AGC sigma-delta output (acts as input only in
production test modes)
I/O
Open
drain
1
5
6
42
Test
For normal operation, this pin must be held at 0V.
I
CMOS
3.3
43
IRQ
Active low interrupt output. Reading all active
interrupt registers resets this pin (acts as input only in
production test modes)
I/O
Open
drain
1
5
6
46
MOSTRT
MPEG output start signal. High during the first byte of
a packet.
O
CMOS
Tri-state
3.3
2
相關PDF資料 |
PDF描述 |
|---|---|
| ZL10312QCG1 | Satellite Demodulator |
| ZL10312UBH | Satellite Demodulator |
| ZL10312 | Satellite Demodulator |
| ZL10313QCG | Augumented Cat. 6 T568A/B Modular Jack; No. of Ports:24; Mounting Type:1U Panel; Approval Categories:Augmented Category 6; Jacks FCC part 68, Subpart F & IEC-603-7 compliant RoHS Compliant: Yes |
| ZL10313QCG1 | Augumented Cat. 6 T568A/B Modular Jack; No. of Ports:48; Mounting Type:2U Panel; Approval Categories:Augmented Category 6; Jacks FCC part 68, Subpart F & IEC-603-7 compliant RoHS Compliant: Yes |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ZL10312QCG1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator |
| ZL10312UBH | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator |
| ZL10313 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator |
| ZL10313QCG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator |
| ZL10313QCG1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Satellite Demodulator |
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