- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373760 > Z5380 (ZiLOG, Inc.) Small Computer System Interface(小型計算機系統(tǒng)接口(SCSI)控制器) PDF資料下載
參數(shù)資料
| 型號： | Z5380 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | Small Computer System Interface(小型計算機系統(tǒng)接口(SCSI)控制器) |
| 中文描述： | 小型計算機系統(tǒng)接口（小型計算機系統(tǒng)接口（的SCSI）控制器） |
| 文件頁數(shù)： | 11/37頁 |
| 文件大小： | 409K |
| 代理商： | Z5380 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
11
Z5380 SCSI
Z
ILOG
PS97SCC0100
The proposed SCSI specification also requires that no
more than two device ID’s be active during the selection
process. To ensure this, the Current SCSI Data Register is
read.
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
14 and 15, respectively.
Figure 14. Bus and Status Register
Figure 15. Current SCSI Bus Status Register
End Of Process (EOP) Interrupt
An End Of Process signal (EOP) which occurs during a
DMA transfer (DMA Mode True) will set the End of DMA
Status bit (bit 7) and will optionally generate an interrupt if
Enable EOP Interrupt bit (Mode Register, bit 3) is True. The
/EOP pulse will not be recognized (End of DMA bit set)
unless /EOP, /DACK, and either /IOR or /IOW are concur-
rently active for at least 100 ns. DMA transfers can still
occur if /EOP was not asserted at the correct time. This
interrupt is disabled by resetting the Enable EOP Interrupt
bit.
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
0
0
0
1
X
0
X
0
D7
D0
D7
D0
/DBP
/SEL
I//O
C//D
/MSG
/REQ
/BSY
/RST
0
0
0
X
X
X
0
X
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register for this interrupt are
shown in Figures 16 and 17.
D7
D0
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
1
0
0
1
0
0
0
X
Figure 16. Bus and Status Register
D7
D0
/DBP
/SEL
I//O
C//D
/MSG
/REQ
/BSY
/RST
0
1
1
X
X
X
0
X
Figure 17. Current SCSI Bus Status Register
The End of DMA bit is used to determine when a block
transfer is complete. Receive operations are complete
when there is no data left in the chip and no additional
handshakes occurring. The only exception to this is receiv-
ing data as an Initiator and the Target opts to send
additional data for the same phase. In this /REQ goes
active and the new data is present in the Input Data
Register. Since a phase-mismatch interrupt will not occur,
/REQ and /ACK need to be sampled to determine that the
Target is attempting to send more data.
相關PDF資料 |
PDF描述 |
|---|---|
| Z53C80 | SMALL COMPUTER SYSTEM INTERFACE (SCSI) |
| Z53C8003PSC | SMALL COMPUTER SYSTEM INTERFACE (SCSI) |
| Z53C8003VSC | SMALL COMPUTER SYSTEM INTERFACE (SCSI) |
| Z53C80SCSI | SMALL COMPUTER SYSTEM INTERFACE (SCSI) |
| Z54122 | RETRIGGERABLE MONOSTABLE MULTIVIBRATOR |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| Z538001PEC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:SMALL COMPUTER SYSTEM INTERFACE (SCSI) |
| Z538001PSC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:SMALL COMPUTER SYSTEM INTERFACE (SCSI) |
| Z538001VEC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:SMALL COMPUTER SYSTEM INTERFACE (SCSI) |
| Z538001VSC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:SMALL COMPUTER SYSTEM INTERFACE (SCSI) |
| Z5380P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
發(fā)布緊急采購，3分鐘左右您將得到回復。