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參數(shù)資料
| 型號： | Z0220516SSCR4292 |
| 英文描述： | Modem Controller |
| 中文描述： | 調(diào)制解調(diào)器控制器 |
| 文件頁數(shù)： | 19/48頁 |
| 文件大?。?/td> | 1331K |
| 代理商： | Z0220516SSCR4292 |
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Z02202
ZiLOG
V.22bis Data Pump with Integrated AFE
PS000902-0501
Z02201
19
Reg7 Data Pump Register 7.
These bits represent the
state of HDLC frames when the data pump is in the
HDLC
FRAMING
mode. These bits are valid only if
BUFCTRL.
bit
7
is
1
. The host should refrain from writing Reg7
to avoid changing the values of bit fields set by the data
pump. Bits not defined above are reserved or not available
for use.
The host reads register Reg7 immediately before
DATAP
.
The two CRC checksum bytes in received
HDLC
frames are
provided to the host.
At any reset, or when the host sets Config register, bits 0–6
(
MODE
) to 0 (
STANDBY
) the data pump sets
TEND
to
0
,
RXERROR
to
0
, and
EOF
to
0
.
Table 13. REG7: HDLC Register
SYMBOL
EOF
POSITION
REG 7, bit 0
NAME AND DESCRIPTION
Receive End of Frame
.
The data pump sets EOF to 1 when an HDLC frame has
been completely received (that is, when frame data has been received and a
closing HDLC
fl
ag or HDLC Abort condition is received). If the frame was
correctly received, the data pump also sets Reg5, bit 1 (RXERROR) to 0, Reg5, bit
bit 6 (RXI) to 1, and DATAP to 7EH. See Reg7, bit 1 (RXERROR) for a description
of CRC errors and HDLC Aborts. EOF re
fl
ects whether the current register DATAP
value indicates the end of receipt of an HDLC frame. When the
fi
rst data byte of
the next HDLC frame is received, or if an HDLC ABORT condition is received
when no HDLC frame data was received, the data pump sets EOF to 0. This
condition may occur only 8 bit times after the data pump sets EOF to 1.
Receive Error. If an HDLC frame contains a CRC error, or an HDLC Abort condition
is received, the data pump sets RXERROR to 1, Reg5, bit 6 (RXI) to 1, and DATAP
to the value of 7EH or FFH. If the frame had a CRC error, DATAP has the value of
7EH. If an HDLC Abort condition was received, DATAP is FFH. RXERROR re
fl
ects
whether the current register DATAP contains an error. When the
fi
rst data byte of
the next HDLC frame is received, the data pump sets RXERROR to 0. This
condition may occur only 8 bit times after the data pump set RXERROR to 1.
Transmit End of Frame
.
The data pump sets TEND to 1 when it closes an HDLC
frame that is transmitted. The data pump sets TEND to 0 after transmitting the
CRC bytes, when it starts transmitting the closing
fl
ag of the HDLC frame. The
data pump closes an HDLC frame when the host does not provide data to
transmit (see DATAP) in time to be included in the HDLC frame.
Unused. Set these bits to 0.
RXERR
REG 7, bit 1
TEND
REG 7, bit 2
0
REG 7,
bits 3
–
7
Note:
1. All the bits in this register (REG 7) default to 0 at power up or after reset.
2. All undefined bits of this register are reserved. The host writes a 0 to all reserved bit positions when writing this register.
The host ignores the reserved bits when reading this register.
Bit
0
0
0
7
6
5
4
3
2
1
0
0
TEND
RXERR
EOF
0
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