參數(shù)資料
型號: Z0220516SSCR4292
英文描述: Modem Controller
中文描述: 調(diào)制解調(diào)器控制器
文件頁數(shù): 17/48頁
文件大?。?/td> 1331K
代理商: Z0220516SSCR4292
Z02202
ZiLOG
V.22bis Data Pump with Integrated AFE
PS000902-0501
Z02201
17
Table 11. REG4: RAM Control Register
SYMBOL
RAMAH
POSITION
REG 4, bit 0
NAME AND DESCRIPTION
RAM Address High Bit.
The most signi
fi
cant bit of the data pump RAM
address. This bit is set to 1 when accessing a data pump RAM address
that is greater than 255, or set to 0 for any value below 255.
Data Pump RAM Access Request Bit.
Set this bit to 1 to request a read or
write of the data pump RAM. The data pump sets this bit to 0 when the
request has been ful
fi
lled.
Data Pump RAM Read/Write Bit.
Set this bit to 0 to request a read of the
data pump RAM or a 1 to request a write of data pump RAM.
Register Request to Send Bit.
A logical OR operation is executed using the
value of the hardware RTS signal received by the data pump on the RTS
pin. The host sets RTS or RTSP to 1 to inform the data pump the host is
transmitting data. To control the data pump using the RTS signal, set
RTSP to 0. To control the data pump using RTSP, hold RTS High.
Select Parallel Data Mode.
Setting this bit selects the parallel data mode.
Resetting it selects the serial data mode.
RAM Interrupt Enable Bit.
Setting this bit allows the data pump to
interrupt the host when a RAM read/write request has been completed.
Receive Data Interrupt Enable Bit, Parallel Data Mode Only.
This bit, when
set, causes the data pump to generate an interrupt whenever the RXI bit
is set.
Transmit Data Interrupt Enable Bit, Parallel Data Mode Only.
This bit,
when set, causes the data pump to generate an interrupt whenever the
TXI bit is set.
Note:
All the bits in this register (REG 4) default to logic 0 at power-up or after reset sequences are completed.
RAMRQ
REG 4, bit 1
RAMRW
REG 4, bit 2
RTSP
REG 4, bit 3
TPDM
REG 4, bit 4
RAMlE
REG 4, bit 5
RXlE
REG 4, bit 6
TXlE
REG 4, bit 7
Bit
TXIE
RXIE
RAMIE
7
6
5
4
3
2
1
0
TPDM
RAMRW RAMRQ
RAMAH
RTSP
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