參數(shù)資料
型號(hào): XS1-G02B-FB144-C4
廠商: XMOS
文件頁數(shù): 2/24頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 16KB OTP 144FBGA
標(biāo)準(zhǔn)包裝: 176
系列: XS1
核心處理器: XCore
芯體尺寸: 32 位雙核
速度: 400MHz
連通性: USB
輸入/輸出數(shù): 88
程序存儲(chǔ)器容量: 16KB(4K x 32)
程序存儲(chǔ)器類型: OTP
RAM 容量: 32K x 32
電壓 - 電源 (Vcc/Vdd): 0.95 V ~ 3.6 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 144-FBGA
包裝: 托盤
其它名稱: 880-1006
XS1-G02B-FB144 Datasheet
9
5.2
Channel Ends, Links and Switch
Threads communicate using point-to-point connections formed between two chan-
nel ends. Between cores, channel communications are implemented over XMOS
Links and routed through switches. The links operate in either 2bit/direction or
5bit/direction mode, depending on the amount of bandwidth required. Circuit
switched, streaming and packet switched data can both be supported eciently.
Streams provide the fastest possible data rates between XCores (up to 250 MBit/s),
but each stream requires a single link to be reserved between switches on two
cores. All packet communications can be multiplexed onto a single link. A total of
eight 5bit links are available between both cores.
Information on the supported routing topologies that can be used to connect
multiple devices together can be found in the XS1-G Link Performance and Design
Guides, document number X2215.
5.3
Ports and Clock Blocks
Ports provide an interface between the threads and I/O pins. The operation of
each port is synchronized to a clock block. A clock block can be connected to an
external clock input, or it can be run from the divided reference clock. A clock
block can also output its signal to a pin. On reset, each port is connected to clock
block 0, which runs from the reference clock.
The ports and links are multiplexed, allowing the pins to be congured for use
by ports of dierent widths or links. If an XMOS Link is enabled, the pins of the
underlying ports are disabled. If a port is enabled, it overrules ports with higher
widths that share the same pins. The pins on the wider port that are not shared
remain available for use when the narrower port is enabled. Ports always operate
at their specied width, even if they share pins with another port.
5.4
Timers
Timers are 32-bit counters that are relative to the reference clock. A timer is
dened to tick every 10 ns. This value is derived from the reference clock, which is
congured to tick at 100 MHz by default.
5.5
SRAM
Each XCore integrates a single 64 KB SRAM bank for both instructions and data. All
internal memory is 32 bits wide, and instructions are either 16-bit or 32-bit. Byte
(8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed
within one core clock cycle. There is no dedicated external memory interface,
although data memory can be expanded through appropriate use of the ports.
Document Number: 1100C
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