參數(shù)資料
型號: XRT91L32IQ-F
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
中文描述: TRANSCEIVER, PQFP100
封裝: 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-100
文件頁數(shù): 20/37頁
文件大?。?/td> 417K
代理商: XRT91L32IQ-F
XRT91L32
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
xr
REV. 1.0.2
18
2.8
The 8-bit Single-Ended LVTTL running at 77.76 Mbps (STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) parallel
data output of the receive path is used to interface to a SONET Framer/ASIC synchronized to the recovered
clock. A simplified block diagram is shown in Figure 9.
Receive Parallel Output Interface
2.9
The parallel receiver outputs are automatically pulled "Low" or forced to a logic state of "0" during a LOS
condition to prevent data chattering unless LOS detection is disabled by asserting DLOSDIS and keeping
LOSEXT input pin "high." In addition, the user can also assert LOSEXT input pin "low" from the optical module
to force an LOS and mute the parallel receiver outputs as well (while DLOSDIS input is also low, see Figure 7.)
Disable Parallel Receive Data Output Upon LOS
F
IGURE
9. R
ECEIVE
P
ARALLEL
O
UTPUT
I
NTERFACE
B
LOCK
SONET Framer/ASIC
XRT91L32
STS-12/STM-4
or
STS-3/STM-1
Transceiver
RXPCLKO
RXDO[7:0]
8
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