參數(shù)資料
型號: XRT91L32IQ-F
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
中文描述: TRANSCEIVER, PQFP100
封裝: 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-100
文件頁數(shù): 13/37頁
文件大?。?/td> 417K
代理商: XRT91L32IQ-F
xr
REV. 1.0.2
XRT91L32
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
11
1.0
FUNCTIONAL DESCRIPTION
The XRT91L32 transceiver is designed to operate with a SONET Framer/ASIC device and provide a high-
speed serial interface to optical networks. The transceiver converts 8-bit parallel data running at 77.76 Mbps
(STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) to a serial Differential LVPECL bit stream at 622.08 Mbps or
155.52 Mbps and vice-versa. It implements a clock multiplier unit (CMU), SONET/SDH serialization/de-
serialization (SerDes), receive clock and data recovery (CDR) unit and a SONET/SDH frame and byte
boundary detection circuit. The transceiver is divided into Transmit and Receive sections and is used to
provide the front end component of SONET equipment, which includes primarily serial transmit and receive
functions.
1.1
STS-12/STM-4 and STS-3/STM-1 Mode of Operation
Functionality of the transceiver can be configured by using the appropriate signal level on the STS-12/STS-3
pin. STS-3/STM-1 mode is selected by pulling STS-12/STS-3 "Low" as described in the Hardware Pin
Descriptions. However, if STS-12/STM-4 mode is desired, it is selected by pulling STS-12/STS-3 "High."
Therefore, the following sections describe the functionality rather than how each function is controlled. Hence,
the hardware Pin and the Register Bit Descriptions focus on device configuration.
1.2
Clock Input Reference for Clock Multiplier (Synthesizer) Unit
The XRT91L32 can accept both a 19.44 MHz or a 77.76 MHz Differential LVPECL clock input at REFCLKP/N
or a Single-Ended LVTTL clock at TTLREFCLK as its internal timing reference for generating higher speed
clocks. The REFCLKP/N or TTLREFCLK input should be generated from an LVPECL/LVTTL crystal oscillator
which has a frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the
necessary accuracy required for SONET systems. The reference clock can be provided with one of two
frequencies chosen by CMUFREQSEL. The reference frequency options for the XRT91L32 are listed in
Table 1.
1.3
Due to different operating modes and data logic paths through the device, there is an associated latency from
data ingress to data egress. Table 2 specifies the data latency for a typical path.
T
ABLE
2: D
ATA
INGRESS
TO
DATA
EGRESS
LATENCY
Data Latency
T
ABLE
1: CMU R
EFERENCE
F
REQUENCY
O
PTIONS
(D
IFFERENTIAL
OR
S
INGLE
-E
NDED
)
CMUFREQSEL
STS12/STS3
REFCLKP/N
OR
TTLREFCLK
REFERENCE
FREQUENCY
D
ATA
R
ATE
0
0
77.76 MHz
STS-3/STM-1
155.52 Mbps
0
1
77.76 MHz
STS-12/STM-4
622.08 Mbps
1
0
19.44 MHz
STS-3/STM-1
155.52 Mbps
1
1
19.44 MHz
STS-12/STM-4
622.08 Mbps
M
ODE
O
F
O
PERATION
D
ATA
P
ATH
C
LOCK
R
EFERENCE
R
ANGE
O
F
C
LOCK
C
YCLES
Thru-mode
MSB at RXIP/N to data on RXDO[7:0]
Recoved RXIP/N Clock
25 to 35
Serial Remote Loopback MSB at RXIP/N to MSB at TXOP/N
Recoved RXIP/N Clock
2 to 4
相關(guān)PDF資料
PDF描述
XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80_0507 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80IB 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81IB 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT91L32IQTR 功能描述:LIN 收發(fā)器 PHY Transceiver RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8
XRT91L32IQTR-F 功能描述:LIN 收發(fā)器 PHY Transceiver RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8
XRT91L33 制造商:EXAR 制造商全稱:EXAR 功能描述:STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
XRT91L33AIG-F 制造商:Exar Corporation 功能描述:CDR 155.52Mbps/622.08Mbps SONET/SDH 20-Pin TSSOP
XRT91L33ES 功能描述:界面開發(fā)工具 Eval System for XRT91L33 Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V