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參數(shù)資料
| 型號(hào)： | XRT86VL34 |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 151/156頁(yè) |
| 文件大小： | 816K |
| 代理商： | XRT86VL34 |
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XRT86VL34
146
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
2
RXMUTE
R/W
0
Receive Output Mute:
This bit permits the user to configure the Receive T1 Block to auto-
matically pull its Recovered Data Output pins to GND anytime (and
for the duration that) the Receive T1 LIU Block declares the LOS
defect condition.
In other words, if this feature is enabled, the Receive T1 LIU Block
will automatically “mute” the Recovered data that is being routed to
the Receive T1 Framer block anytime (and for the duration that) the
Receive T1 LIU Block declares the LOS defect condition.
0 – Disables the “Muting upon LOS” feature.
1 – Enables the “Muting upon LOS” feature.
N
OTE
:
The receive clock is not muted when this feature is enabled.
1
EXLOS
Extended LOS Enable:
This bit allows users to extend the number of zeros at the receive
input of each channel before RLOS is declared.
When Extended LOS is enabled, the Receive T1 LIU Block will
declare RLOS condition when it receives 4096 number of consecu-
tive zeros at the receive input.
When Extended LOS is disabled, the Receive T1 LIU Block will
declare RLOS condition when it receives 175 number of consecu-
tive zeros at the receive input.
0 = Disables the Extended LOS Feature.
1 = Enables the Extended LOS Feature.
0
ICT
R/W
0
In-Circuit-Testing Enable:
This bit allows users to tristate the output pins of all channels for in-
circuit testing purposes.
When In-Circuit-Testing is enabled, all output pins of the
XRT86VL34 are “Tri-stated”. When In-Circuit-Testing is disabled, all
output pins will resume to normal condition.
0 = Disables the In-Circuit-Testing Feature.
1 = Enables the In-Circuit-Testing Feature.
T
ABLE
125: LIU G
LOBAL
C
ONTROL
R
EGISTER
2 (LIUGCR2) H
EX
A
DDRESS
: 0
X
0FE2
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Force to "0"
R/W
0
Set to "0"
6
RxTCNTL
R/W
0
Receive Termination Select Control
This bit sets the LIU to control the RxTSEL function with either the
individual channel register bit or the global hardware pin.
0 = Control of the receive termination is set to the register bits
1 = Control of the receive termination is set to the hardware pin
5-0
Reserved
R/W
0
This Bit Is Not Used
T
ABLE
124: LIU G
LOBAL
C
ONTROL
R
EGISTER
1 (LIUGCR1) H
EX
A
DDRESS
: 0
X
0FE1
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT86VL34_2 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL34IB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL38_2 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL38IB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL38IB484 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86VL34_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION |
| XRT86VL34_1 | 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
| XRT86VL34_2 | 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION |
| XRT86VL34ES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT86VL34IB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4 IND FULL DPLX FIFO TWO-FRAME, CAS, CCS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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