參數(shù)資料
型號(hào)： XRT86VL32
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 77/174頁
文件大?。?/td> 903K
代理商： XRT86VL32
XRT86VL32
72
REV. V1.2.0
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
T
ABLE
58: D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR3) H
EX
A
DDRESS
: 0
X
n153
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Reserved
-
-
Reserved. Please set this bit to’0’ for normal operation.
6
MOS ABORT
Disable
R/W
0
MOS ABORT Disable:
This bit permits the user to either enable or disable the “Automatic MOS
ABORT” feature within Transmit HDLC Controller # 3. If the user enables this
feature, then Transmit HDLC Controller block # 3 will automatically transmit
the ABORT Sequence (e.g., a zero followed by a string of 7 consecutive
“1s”) whenever it abruptly transitions from transmitting a MOS type of mes-
sage, to transmitting a BOS type of message.
If the user disables this feature, then the Transmit HDLC Controller Block # 3
will NOT transmit the ABORT sequence, whenever it abruptly transitions
from transmitting a MOS-type of message to transmitting a BOS-type of
message.
0 - Enables the “Automatic MOS Abort” feature
1 - Disables the “Automatic MOS Abort” feature
5
Rx_FCS_DIS
R/W
0
Receive Frame Check Sequence (FCS) Verification Enable/Disable
This bit permits the user to configure the Receive HDLC Controller Block # 3
to compute and verify the FCS value within each incoming LAPD message
frame.
0 - Enables FCS Verification
1 - Disables FCS Verification
4
AutoRx
R/W
0
Auto Receive LAPD Message
This bit configures the Receive HDLC Controller Block #3 to discard any
incoming BOS or LAPD Message frame that exactly match which is currently
stored in the Receive HDLC1 buffer.
0 = Disables this “AUTO DISCARD” feature
1 = Enables this “AUTO DISCARD” feature.
3
Tx_ABORT
R/W
0
Transmit ABORT
This bit configures the Transmit HDLC Controller Block #3 to transmit an
ABORT sequence (string of 7 or more consecutive 1’s) to the Remote termi-
nal.
0 - Configures the Transmit HDLC Controller Block # 3 to function normally
(e.g., not transmit the ABORT sequence).
1 - Configures the Transmit HDLC Controller block # 3 to transmit the
ABORT Sequence.
相關(guān)PDF資料
PDF描述
XRT86VL32_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL32IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL32_07 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
XRT86VL32_0709 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL32_1 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL32_2 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL32ES 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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