
XRT86VL32
28
REV. V1.2.0
DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
2-0
RxSIGDL[2:0]
R/W
000
Receive Signaling and Datalink Select[2:0]:
These bits specify the destination for the data that is to be extracted via D/E
channel, National Bits in timeslot 0 of the non-FAS frames, and Timeslot 16 in
the outbound frames. The table below presents the settings of these three
RxSIGDL bits in detail.
T
ABLE
9: R
ECEIVE
S
IGNALING
& D
ATA
L
INK
S
ELECT
R
EGISTER
(RSDLSR) H
EX
A
DDRESS
: 0
X
n10C
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
R
X
SIGDL
[2:0]
D/E C
HANNEL
N
ATIONAL
B
ITS
T
IME
S
LOT
16
000
RxFrTD_n or the
RxSer_n
output pin
Data Link
RxSER_n output pin
001
RxFrTD_n or the
RxSer_n
output pin
Data Link
CAS signaling is enabled. Time
Slot 16 can be extracted to any
of the following:
RxSer_n output pin
RSAR Register
(0xn500-0xn51F)
RxOH_n output pin on time
slot 16 only
RxSIG_n output pin on every
time slot
010
RxFrTD_n or the
RxSer_n
output pin
Data Link
forced to All
Ones
Time Slot 16 can be extracted
to any of the following:
RxSer_n output pin
RSAR Register
(0xn500-0xn51F)
RxOH_n output pin on time
slot 16 only
RxSIG_n output pin on time
slot 16 only
011
RxFrTD_n or the
RxSer_n
output pin
Data Link
forced to All
Ones
CAS signaling is enabled. Time
Slot 16 can be extracted to any
of the following:
RxSer_n output pin
RSAR Register
(0xn500-0xn51F)
RxOH_n output pin on time
slot 16 only
RxSIG_n output pin on every
time slot
100
RxSIG_n or the
RxSer_n
output pin
Data Link
RxSER_n output pin
101/110/
111
Not Used
Not Used
Not Used