參數(shù)資料
型號： XRT83SL34
廠商： Exar Corporation
英文描述： QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述： 上海四的T1/E1/J1收發(fā)器時鐘恢復和抖動衰減器
文件頁數(shù)： 76/80頁
文件大?。?/td> 856K
代理商： XRT83SL34
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.8
PRELIMINARY
75
MOTOROLA ASYCHRONOUS INTERFACE TIMING
The signals used in the Motorola microprocessor interface mode are: Address Strobe (AS), Data Strobe (DS),
Read/Write Enable (R/W), Chip Select (CS), Address and Data bits. The interface is compatible with the timing
of a Motorola 68000 microprocessor family with up to 16.67 MHz clock frequency. The interface timing is
shown in Figure 29 and Figure 30. The I/O specifications are shown in Table 50.
FIGURE 29. MOTOROLA 68K ASYNCHRONOUS PROGRAMMED I/O INTERFACE TIMING
TABLE 50: ASYNCHRONOUS - MOTOROLA 68K - INTERFACE TIMING SPECIFICATION
SYMBOL
PARAMETER
MIN
MAX
UNITS
t0
Valid Address to CS Falling Edge
0
-
ns
t1
CS Falling Edge to DS Assert
65
-
ns
t2
DS Assert to DTACK Assert
-
50
ns
NA
DS Pulse Width (t2)
50
-
ns
t3
CS Falling Edge to AS Falling Edge
0
-
ns
Reset pulse width - both Motorola and Intel Operations (see
t9
Reset pulse width
30
FIGURE 30. MICROPROCESSOR INTERFACE TIMING - RESET PULSE WIDTH
CS
A DDR[6:0 ]
DA T A [7 :0 ]
RD_ DS
WR _ R /W
RD Y _ DTA C K
V a lid D a ta fo r Re adbac k
Data A v ailable to W rite In to the LIU
RE AD O PER ATIO N
W RITE O P ERA TIO N
t
0
t
0
t
1
t
2
Va lid Ad d re ss
t
3
t
3
t
1
t
2
AL E_ AS
Reset
t
9
相關(guān)PDF資料
PDF描述
XS2F-A422-90-A 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET
XS2F-A422-A90-A 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET
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XS2F-A422-AC0-A 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET
XS2F-A422-AD0-A 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET
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