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參數(shù)資料
| 型號(hào)： | XRT75R12DIB |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 25/133頁(yè) |
| 文件大小： | 0K |
| 描述： | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 12/12 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 420-LBGA 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 420-TBGA（35x35） |
| 包裝： | 托盤(pán) |
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XRT75R12D
116
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
8.7.2
Wander Measurement Test Results
Wander Measurement test results will be provided in the next revision of the LIU Data Sheet.
8.8
Designing with the LIU
In this section, we will discuss the following topics.
How to design with and configure the LIU to permit a system to meet the above-mentioned Intrinsic Jitter and
Wander requirements.
How is the LIU able to meet the above-mentioned requirements?
How does the LIU permits the user to comply with the SONET APS Recovery Time requirements of 50ms
(per Telcordia GR-253-CORE)?
How should one configure the LIU, if one needs to support "Daisy-Chain" Testing at the end Customer's site?
8.8.1
How to design and configure the LIU to permit a system to meet the above-mentioned
Intrinsic Jitter and Wander requirements
As mentioned earlier, in most application (in which the LIU will be used in a SONET De-Sync Application) the
user will typically interface the LIU to a Mapper device in the manner as presented below in Figure 64.
In this application, the Mapper has the responsibility of receiving a SONET STS-N/OC-N signal and extracting
as many as N DS3 signals from this signal. As a given channel within the Mapper IC extracts out a given DS3
signal (from SONET) it will typically be applying a Clock and Data signal to the "Transmit Input" of the LIU IC.
Figure 64 presents a simple illustration as to how one channel, within the LIU should be connected to the
Mapper IC.
As mentioned above, the Mapper IC will typically output a Clock and Data signal to the LIU. In many cases,
the Mapper IC will output the contents of an entire STS-1 data-stream via the Data Signal to the LIU. However,
the Mapper IC typically only supplies a clock pulse via the Clock Signal to the LIU coincident to whenever a
DS3 bit is being output via the Data Signal. In this case, the Mapper IC would not supply a clock edge
coincident to when a TOH, POH or any non-DS3 data-bit is being output via the Data-Signal.
Figure 64 indicates that the Data Signal from the Mapper device should be connected to the TPDATA_n input
pin of the LIU IC and that the Clock Signal from the Mapper device should be connected to the TCLK_n input
pin of the LIU IC.
In this application, the LIU has the following responsibilities.
FIGURE 64. ILLUSTRATION OF THE LIU BEING CONNECTED TO A MAPPER IC FOR SONET DE-SYNC APPLICATIONS
DS3 to STS-N
Mapper/
Demapper
IC
DS3 to STS-N
Mapper/
Demapper
IC
LIU
STS-N Signal
TPDATA_n input pin
TCLK_n input
De-Mapped (Gapped)
DS3 Data and Clock
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| XRT75R12DIB-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT75R12DIB-L | 功能描述:LIN 收發(fā)器 Synch RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8 |
| XRT75R12ES | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 12CH T3/E3/STS1LIUJA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75R12IB | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 12CH E3/DS3/STS W/JITTER R3 TECH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75R12IB-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 12 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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