TABLE
參數(shù)資料
型號： XRT75R12DIB
廠商： Exar Corporation
文件頁數(shù)： 120/133頁
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 12CH 420TBGA
標準包裝： 40
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 12/12
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 420-LBGA 裸露焊盤
供應商設備封裝： 420-TBGA（35x35）
包裝： 托盤
XRT75R12D
83
REV. 1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TABLE 36: XRT75R12D REGISTER MAP SHOWING JITTER ATTENUATOR CONTROL REGISTERS (JA_N) (N = [0:11])
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
JA RESET
Ch_n
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
R/W
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM7 (M = 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
7 - 4
Reserved
3
JA RESET Ch_n
R/W
Jitter Attenuator RESET - Channel_n:
Writing a "0 to 1" transition within this bit-field will configure the Jitter Attenu-
ator (within Channel_n) to execute a RESET operation.
Whenever the user executes a RESET operation, then following will occur.
The READ and WRITE pointers (within the Jitter Attenuator FIFO) will be
reset to their default values.
The contents of the Jitter Attenuator FIFO will be flushed.
NOTE: The user must follow up any "0 to 1" transition with the appropriate
write operate to set this bit-field back to "0", in order to resume
normal operation with the Jitter Attenuator.
2
JA1 Ch_n
R/W
Jitter Attenuator Configuration Select Input - Bit 1:
This READ/WRITE bit-field, along with Bit 0 (JA0 Ch_n) is used to do any of
the following.
To enable or disable the Jitter Attenuator corresponding to Channel_n.
To select the FIFO Depth for the Jitter Attenuator within Channel_n.
The relationship between the settings of these two bit-fields and the Enable/
Disable States, and FIFO Depths is presented below.
1
JA in Tx Path Ch_n
R/W
Jitter Attenuator in Transmit/Receive Path Select Bit:
This input pin is used to configure the Jitter Attenuator (within Channel_n) to
operate in either the Transmit or Receive path, as described below.
0 - Configures the Jitter Attenuator (within Channel_n) to operate in the
Receive Path.
1 - Configures the Jitter Attenuator (within Channel_n) to operate in the
Transmit Path.
0
JA0 Ch_n
R/W
Jitter Attenuator Configuration Select Input - Bit 0:
See the description for Bit 2 (JA1 Ch_n).
JA0
JA1
Jitter Attenuator Mode
1
Disabled
1
0
SONET/SDH De-Sync Mode
0
1
FIFO Depth = 32 bits
0
FIFO Depth = 16 bits
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