參數(shù)資料
型號(hào)： XRT73L04
廠商： Exar Corporation
英文描述： 4 Channel E3/DS3/STS-1 Line Interface Unit(4通道 E3/DS3/STS-1線接口單元)
中文描述： 4頻道E3/DS3/STS-1線路接口單元（4通道E3/DS3/STS-1線接口單元）
文件頁(yè)數(shù)： 40/62頁(yè)
文件大?。?/td> 781K
代理商： XRT73L04
XRT73L04
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. P1.0.5
á
PRELIMINARY
36
1. If the Receive Equalizer block is turned ON when it
is receiving a line signal over short cable length, the
received line signal may be over-equalized which
could degrade performance by increasing the
amount of jitter that exists in the recovered data
and clock signals or by creating bit-errors
2. The Receive Equalizer has been designed to
counter the frequency-dependent cable loss that a
line signal experiences as it travels from the trans-
mitting terminal to the receiving terminal. However,
the Receive Equalizer was not designed to counter
flat loss where all of the Fourier frequency compo-
nents within the line signal are subject to the same
amount of attenuation. Flat loss is handled by the
AGC block.
Disable the Receive Equalizer block by doing either of
the following.
a. Operating in the Hardware Mode
Setting the REQEN(n) input pin “Low".
b. Operating in the HOST Mode
Writing a "0" to the REQEN(n) bit-field within Com-
mand Register CR2, as illustrated below.
COMMAND REGISTER CR-2 (N)
3.3
The purpose of the Clock Recovery PLL is to track
the incoming Dual-Rail data stream and to derive and
generate a recovered clock signal.
It is important to note that the Clock Recovery PLL re-
quires a line rate clock signal at the EXClk(n) input
pin.
The Clock Recovery PLL operates in one of two
modes:
The Training Mode.
The Data/Clock Recovery Mode
3.3.1
The Training Mode
If a given channel is not receiving a line signal via the
RTIP and RRing input pins, or if the frequency differ-
ence between the line signal and that applied via the
EXClk(n) input pin exceeds 0.5%, then the channel
operates in the Training Mode. When the channel is
operating in the Training Mode, it does the following:
a.
Declare a Loss of Lock indication by toggling its
respective RLOL(n) output pin “High".
b.
Output a clock signal via the RxClk(n) output pins
which is derived from the signal applied to the
EXClk(n) input pin.
3.3.2
The Data/Clock Recovery Mode
If the frequency difference between the line signal
and that applied via the EXClk(n) input pin is less
than 0.5%, then the channel operates in the Data/
Clock Recovery mode. In this mode, the Clock Re-
C
LOCK
R
ECOVERY
PLL
covery PLL locks onto the line signal via the RTIP and
RRing input pins.
3.4
T
HE
HDB3/B3ZS D
ECODER
The Remote Transmitting Terminal typically encodes
the line signal into some sort of Zero Suppression
Line Code (e.g., HDB3 for E3, and B3ZS for DS3 and
STS-1). The purpose of this encoding activity was to
aid in the Clock Recovery process of this data within
the Near-End Receiving Terminal. However, once the
data has made it across the E3, DS3 or STS-1 Trans-
port Medium and has been recovered by the Clock
Recovery PLL, it is now necessary to restore the orig-
inal content of the data. Hence, the purpose of the
HDB3/B3ZS Decoding block is to restore the data
transmitted over the E3, DS3 or STS-1 line to its orig-
inal content prior to Zero Suppression Coding.
3.4.1
B3ZS Decoding (DS3/STS-1 Applications)
If the XRT73L04 is configured to operate in the DS3
or STS-1 Modes, then the HDB3/B3ZS Decoding
Blocks performs B3ZS Decoding. When the Decod-
ers are operating in this mode, each of the Decoders
parses through its respective incoming Dual-Rail data
and checks for the occurrence of either a “00V" or a
"B0V" pattern. If the B3ZS Decoder detects this par-
ticular pattern, then it substitutes these bits with a
"000" pattern.
N
OTE
:
If the B3ZS Decoder detects any bipolar violations
that is not in accordance with the B3ZS Line Code format,
or if the B3ZS Decoder detects a string of 3 (or more) con-
secutive "0’s” in the incoming line signal, then the B3ZS
Decoder flags this event as a Line Code Violation by puls-
ing the LCV output pin “High".
D4
D3
D2
D1
D0
Reserved
Reserved
ALOSDIS(n)
DLOSDIS(n)
REQEN(n)
X
X
X
X
0
相關(guān)PDF資料
PDF描述
XRT73L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L06IB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73LC00A E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73LC00AIV E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73LC03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT73L04A 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L04AIV 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L04B 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L04BES 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT73L04BIV 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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