參數(shù)資料
型號(hào)： XRT73L03BIV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
中文描述： DATACOM, PCM TRANSCEIVER, PQFP120
封裝： 14 X 20 MM, LQFP-120
文件頁(yè)數(shù)： 41/61頁(yè)
文件大?。?/td> 342K
代理商： XRT73L03BIV
XRT73L03B
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
39
Decoder detects this particular pattern, then it substi-
tutes these bits with a “0000" pattern.
Figure 25 illustrates the HDB3 Decoder at work with
two separate Zero Suppression patterns, in the in-
coming Dual-Rail Data Stream.
N
OTE
:
If the HDB3 Decoder detects any bipolar violation
(e.g., "V") pulses that is not in accordance with the HDB3
Line Code format, or if the HDB3 Decoder detects a string
of 4 (or more) "0’s" in the incoming line signal, then the
HDB3 Decoder flags this event as a Line Code Violation by
pulsing the LCV output pin “High".
3.4.3
The XRT73L03B can enable or disable the HDB3/
B3ZS Decoder blocks by either of the following
means.
a. Operating in the HOST Mode
Enable the HDB3/B3ZS Decoder block of Channel(n)
by writing a "0" into the
(SR/DR)_(n)
bit-field within
Command Register CR3-(n), as illustrated below.
Configuring the HDB3/B3ZS Decoder
b. Operating in the Hardware Mode
To globally enable all HDB3/B3ZS Decoder blocks in
the XRT73L03B, pull the ENDECDIS input pin “Low".
To globally disable all HDB3/B3ZS Decoder blocks in
the XRT73L03B and configure the XRT73L03B to
transmit and receive in an AMI format, pull the END-
ECDIS input pin "High".
3.5
LOS D
ECLARATION
/C
LEARANCE
Each channel of the XRT73L03B contains circuitry
that monitors the following two parameters associat-
ed with the incoming line signals.
1.
The amplitude of the incoming line signal via the
RTIP and RRing inputs.
2.
The number of pulses detected in the incoming
line signal within a certain amount of time.
If a given channel of the XRT73L03B determines that
the incoming line signal is missing due to either insuf-
ficient amplitude or a lack of pulses in the incoming
line signal, it declares a Loss of Signal (LOS) condi-
tion. The channel declares the LOS condition by tog-
gling its respective RLOS_(n) output pin “High” and
by setting its corresponding RLOS_(n) bit field in
Command Register 0 or Command Register 8 to "1".
Conversely, if the channel determines that the incom-
ing line signal has been restored (e.g., there is suffi-
cient amplitude and pulses in the incoming line sig-
nal), it clears the LOS condition by toggling its re-
spective RLOS_(n) output pin "Low" and setting its
corresponding RLOS_(n) bit-field to "0".
In general, the LOS Declaration/Clearance scheme
that is employed in the XRT73L03B is based upon
F
IGURE
25. A
N
E
XAMPLE
OF
HDB3 D
ECODING
Data
0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1
0 0 0 V
Line Signal
B 0 0 V
RPOS
RNEG
RCLK
COMMAND REGISTER CR2-(n)
D4
D3
D2
D1
D0
Reserved
ENDECDIS_(n)
ALOSDIS_(n)
DLOSDIS_(n)
REQEN_(n)
X
0
X
X
1
相關(guān)PDF資料
PDF描述
XRT73L04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L04AIV 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L04BIV 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L04 4 Channel E3/DS3/STS-1 Line Interface Unit(4通道 E3/DS3/STS-1線接口單元)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT73L03BIV-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT73L03IV 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT
XRT73L03IVS 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
XRT73L04A 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L04AIV 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
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