參數(shù)資料
型號: XRT73L03BIV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PQFP120
封裝: 14 X 20 MM, LQFP-120
文件頁數(shù): 27/61頁
文件大?。?/td> 342K
代理商: XRT73L03BIV
XRT73L03B
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
25
redundancy to quickly switch out a defective line card
and switch-in the back-up line card.
1.0
Each channel within the XRT73L03B can be config-
ured to support the E3 (34.368 Mbps), DS3 (44.736
Mbps) or the SONET STS-1 (51.84 Mbps) rates. Fur-
ther, each channel can be configured to operate in a
mode/data rate that is independent of the other chan-
nels.
Two methods are available to select the data rate for
each channel of the XRT73L03B.
SELECTING THE DATA RATE
1.1
For the following disscussion the reader should refer
toTable 2 to determine the appropriate Address for
each command register of each channel in the
XRT73L03B. The command register description re-
fers to CR(x)-(n), where (x) = 0 to 7 and (n) refers to a
particular channel of the XRT73L03B.
C
ONFIGURING
C
HANNEL
(n)
F
IGURE
13. F
UNCTIONAL
B
LOCK
D
IAGRAM
OF
THE
XRT73L03B
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF_(n)
Channel 2 - (n) = 2
AGC/
Equalizer
Serial
Processor
Interface
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
Channel 0 - (n) = 0
Channel 1 - (n) = 1
Notes: 1. (n) = 0, 1, or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Device
Monitor
MTIP_(n)
MRing_(n)
DMO_(n)
Transmit
Logic
Duty Cycle Adjust
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
E3_(n)
STS-1/DS3_(n)
Host/(HW)
RLOL_(n)
EXClk_(n)
RxOFF
RxClkINV
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
Tx
Control
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