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XRT72L52
96
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. 1.0.3
NOTE: Once the user has commanded the LAPD Transmitter to start transmission, the LAPD Transmitter will repeat the
above-mentioned process once each second and will insert flag sequence octets into the outbound LAPD channel,
during the idle periods between transmissions.
Bit 2 - TxDL Busy
This Read-Only bit-field permits the user to poll or monitor the status of the LAPD Transmitter to see if it has
completed its transmission of the LAPD Message frame. The LAPD Transmitter will set this bit-field to "1",
while it is in the process of transmitting the LAPD Message frame. However, the LAPD Transmitter will clear
this bit-field to "0" once it has completed its transmission of the LAPD Message frame.
Bit 1 - TxLAPD Interrupt Enable
This Read/Write bit-field permits the user to enable or disable the LAPD Message frame Transmission
Complete interrupt.
Writing a "0" to this bit-field disables this interrupt. Writing a "1" to this bit-field enables this interrupt.
Bit 0 - TxLAPD Interrupt Status
This Reset-upon-Read bit-field permits the user to determine if the LAPD Message Frame Transmission
Complete interrupt has occurred since the last read of this register. If this bit-field contains a "1" then the LAPD
Message Frame Transmission Complete interrupt has occurred since the last read of this register. Conversely,
if this bit-field contains a "0" then it has not.
2.3.6.4
Transmit E3 GC Byte Register (E3, ITU-T G.832)
This Read/Write byte-field permits the user to specify the contents of the GC byte-field in each outbound E3
frame.
NOTE: The contents of this register is ignored, if the LAPD Transmitter is enabled and has been configured to insert the
comprising octets of an outbound LAPD Message frame into the GC byte-field of each outbound E3 frame (e.g., if
DLinNR = "0").
2.3.6.5
Transmit E3 MA Byte Register (E3, ITU-T G.832)
The bit-format of the TxE3 MA Byte register depends upon whether the channel has been configured to
support the November 1995 or the October 1998 revision of the ITU-T G.832 framing format for E3.
The bit-format of the TxE3 MA Byte register, for each of these cases is discussed below.
2.3.6.5.1
The November 1995 Revision
If the channel has been configured to support the November 1995 revision of the ITU-T G.832 Framing Format
for E3, then the bit-format of the TxE3 MA Byte register is as presented below.
TXE3 GC BYTE REGISTER (ADDRESS = 0X35)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxGC[7:0]
R/W
0
TXE3 MA BYTE REGISTER (ADDRESS = 0X36)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit MA Byte
FERF
FEBE
Payload Type
Payload Dependent
Timing
Marker