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XRT72L52
205
REV. 1.0.3
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
NOTE: The Receive DS3 Framer block will also generate the Change in LOS Condition interrupt, when it clears the LOS
Condition.
The Framer chip allows the user to modify the LOS Declaration criteria such that an LOS condition is declared
only if the RLOS input pin (from the XRT73L00 DS3/E3/STS-1 LIU IC) is asserted. In this case, the internally-
generated LOS criteria of 180 consecutive “zeros” will be disabled. This can be accomplished by writing a "0"
to bit 5 (Internal LOS Enable) of the Framer Operating Mode Register, as depicted below.
NOTE: For more information on the RLOS input pin, please see Section 2.1.
4.3.2.5.2
The Alarm Indication Signal (AIS)
The Receive DS3 Framer block will identify and declare an AIS condition if it detects all of the following
conditions in the incoming DS3 Data Stream:
Valid M-bits, F-bits and P-bits
All C-bits are zeros.
X-bits are set to 1
The Payload portion of the DS3 Frame exhibits a repeating 1010... pattern.
The Receive DS3 Framer block contains, within its circuitry, an Up/Down Counter that supports the assertion
and negation of the AIS condition. This counter begins with the value of 0x00 upon power up or reset. The
counter is then incremented anytime the Receive DS3 Framer block detects an AIS Type M-frame. This
counter is then decremented, or kept at zero value, when the Receive DS3 Framer block detects a non-AIS
type M-frame. The Receive DS3 Framer block will declare an AIS Condition if this counter reaches the value
of 63 M-frames or greater. Explained another way, the AIS condition is declared if the number of AIS-type M-
frames is detected, such that it meets the following conditions:
NAIS - NVALID > 63
where:
NAIS = the number of M-frames containing the AIS pattern.
NVALID = the number of M-frames not containing the AIS pattern
If at anytime, the contents of this Up/Down counter exceeds 63 M-frames, then the Receive DS3 Framer block
will:
1. Assert the RxAIS output pin by toggling it "High".
2. Set Bit 7 (RxAIS) within the Rx DS3 Configuration and Status Register, to "1" as depicted below.
FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Local Loop-back
DS3/E3
Internal LOS
Enable
RESET
Interrupt
Enable Reset
Frame Format
TimRefSel[1:0]
R/W
X
1
0
X
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
RxAIS
RxLOS
RxIdle
RxOOF
Reserved
Framing on
Parity
F-Sync Algo
M-Sync Algo