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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
XRT71D03
PRELIMINARY
I
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................. 1
F
EATURES
................................................................................................................................................... 1
A
PPLICATIONS
............................................................................................................................................. 1
Figure 1. Block Diagram (one Channel) ................................................................................................ 1
Figure 2. Pin Out of the XRT71D03 ........................................................................................................ 2
ORDERING INFORMATION ..................................................................................................................... 2
PIN DESCRIPTIONS ........................................................................................................... 4
SYSTEM DESCRIPTION ................................................................................................... 10
Figure 3. Illustration of a typical Channel-n of the XRT71D03 configured to operate in the Hardware
Mode ........................................................................................................................................ 10
Figure 4. Illustration of of a typical Channel-n of the XRT71D03 (configured to operate in the Host
Mode) ....................................................................................................................................... 11
B
ACKGROUND
I
NFORMATION
: ..................................................................................................................... 11
Figure 5. Category 1 DS3 Jitter Transfer Mask .................................................................................. 12
JITTER ATTENUATION: ......................................................................................................................... 12
Figure 6. XRT71D03 Desynchronizer Block Diagram ........................................................................ 13
T
ABLE
1: F
UNCTIONS
OF
DUAL
MODE
PINS
IN
H
ARDWARE
M
ODE
CONFIGURATION
..................................... 13
Host Mode:................................................................................................................................................ 13
T
ABLE
2: A
DDRESS
AND
B
IT
F
ORMATS
OF
THE
C
OMMAND
R
EGISTERS
...................................................... 14
Serial Interface Operation.......................................................................................................................... 14
Bit 1—R/W (Read/Write) Bit....................................................................................................................... 14
Bit 7:........................................................................................................................................................... 14
Bit 8—A6.................................................................................................................................................... 14
Read Operation.......................................................................................................................................... 14
Write Operation.......................................................................................................................................... 14
Figure 7. Microprocessor Serial Interface Data Structure ................................................................. 15
Simplified Interface Option......................................................................................................................... 15
Figure 8. Timing Diagram for the Microprocessor Serial Interface .................................................. 15
Figure 9. Input/Output Timing .............................................................................................................. 16
T
ABLE
3: XRT71D03 J
ITTER
T
RANSFER
F
UNCTION
.................................................................................. 16
T
ABLE
4: XRT71D03 M
AXIMUM
J
ITTER
T
OLERANCE
................................................................................. 18
ORDERING INFORMATION ............................................................................................. 19
PACKAGE DIMENSIONS ................................................................................................. 19
R
EVISION
H
ISTORY
..................................................................................................................................... 20