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參數(shù)資料
| 型號： | XRK799J93 |
| 廠商： | Exar Corporation |
| 英文描述： | INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER |
| 中文描述： | 智能動態(tài)時鐘開關(guān)PLL時鐘驅(qū)動器 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 76K |
| 代理商： | XRK799J93 |
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XRK799J93
REV. 1.0.1
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
3
PIN DESCRIPTIONS
P
IN
N
AME
T
YPE
D
ESCRIPTION
CLK0, CLK0
CLK1, CLK1
LVPECL Input
LVPECL Input
Clock 0 - Differential PLL clock reference (CLK0 pulldown, CLK0 pulldown)
Clock 1 - Differential PLL clock reference (CLK1 pulldown, CLK1 pulldown)
Ext_FB, Ext_FB
LVPECL Input
Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pulldown)
Qa[1:0], Qa[1:0]
LVPECL Output
Differential 1x output pairs, connect one QaX pair to Ext_FB
Qb[2:0], Qb[2:0]
LVPECL Output
Differential 2x output pairs
Inp0bad
LVCMOS Output
Indicates detection of a bad input reference Clock 0 with respect to the feed-
back signal. The output is active HIGH and will remain HIGH until the alarm
reset is asserted.
Inp1bad
LVCMOS Output
Indicates detection of a bad input reference Clock 1 with respect to the feed-
back signal. The output is active HIGH and will remain HIGH until the alarm
reset is asserted.
CLK_Selected
LVCMOS Output
0 - if CLK0 is selected
1 - if CLK1 is selected
Alarm_Reset
LVCMOS Input
0 - will reset the input bad flags and align CLK_Selected with Sel_CLK. The
input is one-shotted
1 - normal operation (50K
Ω
pullup).
Sel_CLK
LVCMOS Input
0 - selects CLK0
1 - selects CLK1 (50k
Ω
pulldown)
Man_Override
LVCMOS Input
0 - normal operation
1 - disables internal clock switch circuitry (50K
Ω
pulldown).
PLL_En
LVCMOS Input
0 - bypasses the phase-locked loop, input CLKx directly drives divider block
1 - selected input reference applied to PLL (50K
Ω
pullup).
MR
LVCMOS Input
0 - resets the internal dividers forcing outputs LOW. Asynchronous to the clock
1 - normal operation (50K
Ω
pullup).
VCCA
Power Supply
PLL power supply
VCC
Power Supply
Digital power supply
GNDA
Power Supply
PLL Ground
GND
Power Supply
Digital Ground
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