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參數(shù)資料
| 型號(hào)： | XRK799J93IQ |
| 廠商： | EXAR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER |
| 中文描述： | 799J93 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, TQFP-32 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大小： | 76K |
| 代理商： | XRK799J93IQ |
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
xr
XRK799J93
INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER
DECEMBER 2006
GENERAL DESCRIPTION
REV. 1.0.1
The XRK799J93 is a PLL clock driver designed
specifically for redundant clock tree designs. The
device receives two differential LVPECL clock signals
from which it generates 5 new differential LVPECL
clock outputs. Two of the output pairs regenerate the
input signals frequency and phase while the other
three pairs generate 2x, phase aligned clock outputs.
External PLL feedback is used to also provide zero
delay buffer performance.
The XRK799J93 Intelligent Dynamic Clock Switch
circuit continuously monitors both input CLK signals.
Upon detection of a failure (CLK stuck HIGH or LOW
for at least 1 period), the INP_BAD for that CLK will
be latched (H). If that CLK is the primary clock, the
device will switch to the good secondary clock and
phase/frequency alignment will occur with minimal
output phase disturbance. The typical phase bump
caused by a failed clock is eliminated.
FEATURES
Fully Integrated PLL
Intelligent Dynamic Clock Switch
LVPECL Clock Outputs
LVCMOS Control I/O
3.3V Operation
32-Lead TQFP Packaging
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRK799J93
÷2
÷4
PLL
CLK0
CLK0
CLK1
CLK1
Ext_FB
Ext_FB
MR
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
Qa0
Qa0
Qa1
Qa1
Dynamic
Switch
Logic
CLK_Selected
INP1Bad
INP0Bad
Man_Override
Alarm_Reset
Sel_CLK
160-380MHz
PLL_En
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