參數(shù)資料
型號： XR68C92IJTR-F
廠商： Exar Corporation
文件頁數(shù)： 9/33頁
文件大?。?/td> 0K
描述： DUAL CHANNEL UART 44PLCC
標準包裝： 500
特點： *
通道數(shù)： 2，DUART
FIFO's： 16 字節(jié)
電源電壓： 2.97 V ~ 5.5 V
帶自動流量控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應商設備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
XR68C92/192
17
Rev. 1.33
MODE REGISTER 0 (MR0A, MR0B)
This register is accessed only when command is
applied via CRA, CRB register (upper nibble = 0xB).
After reading or writing to MR0A (or MR0B) register,
the mode register pointer will point to MR1A (or MR1B)
register.
MR0A Bit-0:
Extended baud rate table selection for both channels.
0 = Normal baud rate tables
1 = Extended baud rate tables 1
MR0A Bit-1: Special Function.
0 = Normal
1 = Factory test mode
MR0A Bit-2:
Extended baud rate table selection for both channels.
0 = Normal baud rate tables
1 = Extend baud rate tables 2
MR0A Bit-3, MR0B Bits 3-0:
Not Used. Any write to this bit is ignored.
MR0A, MR0B Bits 5-4:
Transmit trigger level select.
Bit-5
Bit-4
XR68C92
0
8 FIFO locations empty (default)
0
1
4 FIFO locations empty
1
0
6 FIFO locations empty
1
1 FIFO location empty
Bit-5
Bit-4
XR68C192
0
16 FIFO locations empty (default)
0
1
6 FIFO locations empty
1
0
12 FIFO locations empty
1
1 FIFO location empty
MR0A, MR0B Bit-6:
Receive trigger level select. This bit is associated with
MR1 Bit-6.
MR0 Bit-6
MR1 Bit-6
XR68C92
0
1 byte in FIFO (default)
0
1
3 bytes in FIFO
1
0
6 bytes in FIFO
1
8 bytes in FIFO
MR0 Bit-6
MR1 Bit-6
XR68C192
0
1 byte in FIFO (default)
0
1
6 bytes in FIFO
1
0
12 bytes in FIFO
1
16 bytes in FIFO
MR0A, MR0B Bit-7:
Receive time-out (watch dog timer).
0 = Disabled (default)
1 = Enabled
See description under 'Watchdog Timer'.
MODE REGISTER 1 (MR1A, MR1B)
MR1A, MR1B are accessed after reset or by command
applied via CRA, CRB register (upper nibble = 0x1).
After reading or writing to MR1A (or MR1B) register,
the mode register pointer will point to MR2A (or MR2B)
register.
MR1A, MR1B Bits 1-0:
Character Length
0 0 = 5 (default)
1 0 = 7
0 1 = 6
1 1 = 8
MR1A, MR1B Bit-2:
In non-Multidrop mode, this bit selects the parity.
0 = Even Parity (default)
1 = Odd Parity
In Multidrop mode, this bit is the Address/Data flag.
0 = Data (default)
1 = Address
MR1A, MR1B Bit 4-3: Parity mode.
00 = With parity (default)
10 = No parity
01 = Force parity
11 = Multidrop mode
MR1A, MR1B Bit-5: Data error mode.
0 = Single Character mode (default)
1 = Block (FIFO) mode
MR1A, MR1B Bit-6.
Receive trigger levels. See description under MR0 bit-
6.
MR1A, MR1B Bit-7: Receive RTS flow control.
0 = No RX RTS control function (default)
1 = Auto RX RTS control function
The output OP0 (OP1) serves as the -RTS signal for
channel A (channel B). Note that MR2 A/B bit-5 also
controls OP0 (OP1). Only one of MR1 bit-7 or MR2 bit-
5 should be set to '1'.
MODE REGISTER 2 (MR2A, MR2B)
This register is accessed
after any read or write
operation to MR1A (or MR1B) register is performed.
Any read or write to MR2A (or MR2B) does not change
the mode register pointer. User should use one of the
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