參數(shù)資料
型號: XR20M1172IG28
廠商: Exar Corporation
文件頁數(shù): 33/55頁
文件大?。?/td> 0K
描述: IC UART FIFO I2C/SPI 64B 28TSSOP
產(chǎn)品變化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
標(biāo)準(zhǔn)包裝: 50
特點: *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 1.62 V ~ 3.63 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
XR20M1172
39
REV. 1.2.0
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
4.19
Extra Features Control Register (EFCR) - Read/Write
EFCR[7]: IrDA mode
This bit selects between the slow and fast IrDA modes. See “Section 2.15, Infrared Mode” on page 22 for
complete details.
Logic 0 = IrDA version 1.0, 3/16 pulse ratio, data rate up to 115.2 Kbps
Logic 1 = IrDA version 1.1, 1/4 pulse ratio, data rate up to 1.152 Mbps
EFCR[6]: Reserved
EFCR[5]: Auto RS-485 Polarity Inversion
This bit changes the polarity of the Auto RS-485 Half-Duplex Direction Control output (RTS#). This bit will only
affect the behavior of the RTS# output if EFCR[4] = 1. See “Section 2.14, Auto RS485 Half-duplex Control”
on page 20 for complete details.
Logic 0 = RTS# output is LOW when transmitting and HIGH when receiving.
Logic 1 = RTS# output is HIGH when transmitting and LOW when receiving.
EFCR[4]: Auto RS-485 Enable
This bit enables the RTS# output as the Auto RS-485 Half-Duplex Direction Control output. See “Section
2.14, Auto RS485 Half-duplex Control” on page 20 for complete details.
Logic 0 = RTS# output can be used for Auto RTS Hardware Flow Control or as a general purpose output.
Logic 1 = RTS# output enabled as the Auto RS-485 Half-Duplex Direction Control output.
EFCR[3]: Reserved
EFCR[2]: Transmitter Disable
UART does not send serial data out on the TX output pin, but the TX FIFO will continue to receive data from
CPU until full. Any data in the TSR will be sent out before the trasnmitter goes into disable state.
Logic 0 = Transmitter is enabled
Logic 1 = Transmitter is disabled
EFCR[1] = Receiver Disable
UART will stop receiving data immediately once this bit is set to a Logic 1. Any data that is being received in
the TSR will be received correctly and sent to the RX FIFO.
Logic 0 = Receiver is enabled
Logic 1 = Receiver is disabled
EFCR[0]: 9-bit or Multidrop Mode Enable
This bit enables 9-bit or Multidrop mode. See “Section 2.14, Auto RS485 Half-duplex Control” on page 20
for complete details.
Logic 0 = Normal 8-bit mode
Logic 1 = Enable 9-bit or Multidrop mode
4.20
Baud Rate Generator Registers (DLL, DLM and DLD[3:0]) - Read/Write
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. SEE”PROGRAMMABLE BAUD RATE GENERATOR WITH
FRACTIONAL DIVISOR” ON PAGE 13.
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