參數(shù)資料
型號: XR20M1172IG28
廠商: Exar Corporation
文件頁數(shù): 28/55頁
文件大小: 0K
描述: IC UART FIFO I2C/SPI 64B 28TSSOP
產(chǎn)品變化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
標準包裝: 50
特點: *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 1.62 V ~ 3.63 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 28-TSSOP
包裝: 管件
XR20M1172
34
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
REV. 1.2.0
MCR[2]: OP1# / TCR and TLR Enable
OP1# is not available as an output pin on the M1172. But it is available for use during Internal Loopback Mode
(MCR[4] = 1). In the Internal Loopback Mode, this bit is used to write the state of the modem RI# interface
signal.
This bit is also used to select between the MSR and TCR registers at address offset 0x6 and the SPR and TLR
registers at address offset 0x7. Table 12 and Table 13 below shows how these registers are accessed.
MCR[3]: OP2#
OP2# is not available as an output pin on the M1172 but can be controlled in Internal Loopback Mode (MCR[4]
= 1).
Logic 0 = OP2# set HIGH(default).
Logic 1 = OP2# set LOW.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 19.
MCR[5]: Xon-Any Enable (requires EFR bit-4=1 to write to this bit)
Logic 0 = Disable Xon-Any function (default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the M1172 is programmed to use the Xon/Xoff flow control.
MCR[6]: IR Mode Enable (requires EFR bit-4=1 to write to this bit)
This bit enables the infrared mode and/or controls the infrared mode after power-up. See “Section 2.15,
Infrared Mode” on page 22 for complete details.
Logic 0 = Reserved (default).
Logic 1 = Enable IR Mode.
TABLE 12: REGISTER AT ADDRESS OFFSET 0X6
EFR[4]
MCR[2] Register at Address Offset 0x6
0
X
Modem Status Register (MSR)
1
0
Modem Status Register (MSR)
1
Trigger Control Register (TCR)
TABLE 13: REGISTER AT ADDRESS OFFSET 0X7
EFR[4]
MCR[2] Register at Address Offset 0x7
0
X
Scratchpad Register (SPR)
1
0
Scratchpad Register (SPR)
1
Trigger Level Register (TLR)
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