參數(shù)資料
型號(hào): XR20M1172IG28
廠商: Exar Corporation
文件頁(yè)數(shù): 3/55頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO I2C/SPI 64B 28TSSOP
產(chǎn)品變化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
標(biāo)準(zhǔn)包裝: 50
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
XR20M1172
11
REV. 1.2.0
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
The 64 byte TX FIFO can be loaded with data or 64 byte RX FIFO data can be unloaded in one SPI write or
read sequence.
After the last read or write transaction, the SPI master will set the SCL signal back to its idle state (LOW).
2.2
Device Reset
The RESET# input resets the internal registers and the serial interface outputs in the UART to its default state
(see Table 16). An active low pulse of longer than 40 ns duration will be required to activate the reset function
in the device.
2.3
Internal Registers
The M1172 has a set of enhanced registers for control, monitoring and data loading and unloading. The
configuration register set is compatible to the industry standard ST16C550. These registers function as data
holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR),
receive line status and control registers (LSR/LCR), modem status and control registers (MSR/MCR),
programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a user accessible Scratchpad Register
(SPR).
Beyond the general 16C550 features and capabilities, the M1172 offers enhanced feature registers (EFR, Xon/
Xoff 1, Xon/Xoff 2, TCR, TLR, TXLVL, RXLVL, IODir, IOState, IOIntEna, IOControl, EFCR and DLD) that
provide automatic RTS and CTS hardware flow control, Xon/Xoff software flow control, automatic RS-485 half-
duplex direction output enable/disable, TX and RX FIFO level counters, and programmable FIFO trigger level
control. For complete details, see “Section 3.0, UART Internal Registers” on page 25.
FIGURE 9. SPI FIFO WRITE
FIGURE 10. SPI FIFO READ
R/W A3
A2
A1
A0
0
CH
X
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SO
last bit
SCLK
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
last bit
R/W A3
A2
A1
A0
0
CH
X
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