參數(shù)資料
型號： XR19L212IL48-F
廠商： Exar Corporation
文件頁數(shù)： 52/52頁
文件大?。?/td> 0K
描述： IC UART/TXRX RS232 48QFN
標(biāo)準(zhǔn)包裝： 260
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232
電源電壓： 3.3 V ~ 5.5 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-QFN-EP（7x7）
包裝： 托盤
XR19L212
9
REV. 1.0.1
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
Beyond the general 16C550 features and capabilities, the L212 offers enhanced feature registers such as
EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, EMSR and FC that provide automatic RTS and CTS hardware flow
control, Xon/Xoff software flow control, FIFO trigger level control and FIFO level counters. All the register
functions are discussed in full detail later in “Section 3.0, UART Internal Registers” on page 22.
2.7
DMA Mode
The DMA Mode (a legacy term) refers to data block transfer operation. The DMA mode affects the state of the
RXRDY# and TXRDY# output pins available in the original 16C550. These pins are not available in the
XR19L212. The DMA Enable bit (FCR bit-3) does not have any function in this device and can be a ’0’ or a ’1’.
2.8
INT (IRQ#) Output
The interrupt output changes according to the operating mode and enhanced features setup. Table 3 and
Table 4 below summarize the operating behavior for the transmitter and receiver in the Intel and Motorola
modes. Also see Figures 19 through 22.
2.9
Crystal or External Clock Input
The L212 includes an on-chip oscillator (XTAL1 and XTAL2) to generate a clock when a crystal is connected
between the XTAL1 and XTAL2 pins of the device. Alternatively, an external clock can be supplied through the
XTAL1 pin. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock input and XTAL2 pin is the bufferred output which can be used as a clock signal for
other devices in the system. Please note that the input XTAL1 is not 5V tolerant and therefore, the maximum
TABLE 3: INT (IRQ#) PIN OPERATION FOR TRANSMITTER
FCR BIT-0 = 0 (FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin
(I/M# = 1)
0 = one byte in THR
1 = THR empty
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO empty
IRQ# Pin
(I/M# = 0)
1 = one byte in THR
0 = THR empty
1 = FIFO above trigger level
0 = FIFO below trigger level or FIFO empty
TABLE 4: INT (IRQ#) PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
INT Pin
(I/M# = 1)
0 = no data
1 = 1 byte
0 = FIFO below trigger level
1 = FIFO above trigger level
IRQ# Pin
(I/M# = 0)
1 = no data
0 = 1 byte
1 = FIFO below trigger level
0 = FIFO above trigger level
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