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參數(shù)資料
| 型號： | XR19L212IL48-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 31/52頁 |
| 文件大小： | 0K |
| 描述： | IC UART/TXRX RS232 48QFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 特點： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS232 |
| 電源電壓： | 3.3 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN-EP（7x7） |
| 包裝： | 托盤 |
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XR19L212
37
REV. 1.0.1
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
FCTR[6]: Scratchpad Swap
Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.
Logic 1 = FIFO Level Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced
Mode Select Register is selected when it is written into.
FCTR[7]: Programmable Trigger Register Select
If using both programmable TX and RX trigger levels, TX trigger levels must be set before RX trigger levels.
Logic 0 = Registers TRG and FC selected for RX.
Logic 1 = Registers TRG and FC selected for TX.
4.19
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0
No TX and RX flow control (default and reset)
0
X
No transmit flow control
1
0
X
Transmit Xon1, Xoff1
0
1
X
Transmit Xon2, Xoff2
1
X
Transmit Xon1 and Xon2, Xoff1 and Xoff2
X
0
No receive flow control
X
1
0
Receiver compares Xon1, Xoff1
X
0
1
Receiver compares Xon2, Xoff2
1
0
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
1
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
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| XR19L212IL48TR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 64Byte FIFO 5V 48-Pin QFN EP T/R 制造商:Exar Corporation 功能描述:XR19L212IL48TR-F |
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