- 您現(xiàn)在的位置：買賣IC網 > PDF目錄16512 > XR19L210IL40-0B-EB (Exar Corporation)EVAL BOARD FOR XR19L202 40QFN PDF資料下載
參數(shù)資料
| 型號： | XR19L210IL40-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 15/43頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR19L202 40QFN |
| 標準包裝： | 1 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
XR19L210
22
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.2
IER[7]: CTS Input Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the CTS interrupt (default).
Logic 1 = Enable the CTS interrupt. The UART issues an interrupt when CTS pin makes a transition from low
to high.
4.5
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 7, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.5.1
Interrupt Generation:
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty.
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of a Xoff or Special character.
CTS is when the CTS pin is de-asserted during auto CTS flow control enabled by EFR bit-7.
RTS is when the RTS pin is de-asserted during auto RTS flow control enabled by EFR bit-6.
Wake-up Interrupt is when the device wakes up from sleep mode. See Sleep Mode section for more details.
4.5.2
Interrupt Clearing:
LSR interrupt is cleared by reading the LSR register (but FIFO error bit does not clear until the character(s)
that generated the interrupt(s) is (are) read from the FIFO).
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading the RHR register.
TXRDY interrupt is cleared by reading the ISR register or writing to the THR register.
MSR interrupt is cleared by reading the MSR register.
Xoff interrupt is cleared by reading the ISR or when Xon character(s) is received.
Special character interrupt is cleared by reading the ISR or after the next character is received.
RTS and CTS flow control interrupts are cleared by reading the MSR register.
Wake-up interrupt is cleared by reading the ISR register.
相關PDF資料 |
PDF描述 |
|---|---|
| VI-252-EX | CONVERTER MOD DC/DC 15V 75W |
| 5504972-4 | CABLE ASSEM FIBER SC-ST 5 METER |
| ILSB1206ER6R8K | INDUCTOR 6.8UH 10% 1206 |
| EBC31DRTS-S13 | CONN EDGECARD 62POS .100 EXTEND |
| ILSB1206ER68NM | INDUCTOR 0.068UH 20% 1206 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XR19L210IL40-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR19L212 | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER |
| XR19L212IL48 | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER |
| XR19L212IL48-0B-EB | 功能描述:界面開發(fā)工具 Supports L212 48 pin QFN, PCI Interface RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR19L212IL48-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。