REV. 1.0.4 MSR[3]: Delta CD# Input Flag Logic 0 = " />
參數(shù)資料
型號: XR17V358IB176-F
廠商: Exar Corporation
文件頁數(shù): 54/68頁
文件大?。?/td> 0K
描述: IC UART PCIE OCTAL 176FPBGA
產(chǎn)品培訓(xùn)模塊: PCIe UARTs
UART Product Overview
標準包裝: 160
特點: *
通道數(shù): 1,UART
FIFO's: 256 字節(jié)
規(guī)程: RS485
電源電壓: 1.2V,3.3V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 176-LFBGA
供應(yīng)商設(shè)備封裝: 176-FPBGA(13x13)
包裝: 托盤
配用: 1016-1296-ND - EVAL BOARD FOR XR17V358-E8
1016-1295-ND - EVAL BOARD FOR XR17V358-E4
1016-1293-ND - EVAL BOARD FOR XR17V358
其它名稱: 1016-1294
XR17V358
58
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
REV. 1.0.4
MSR[3]: Delta CD# Input Flag
Logic 0 = No change on CD# input (default).
Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit [3]).
MSR[2]: Delta RI# Input Flag
Logic 0 = No change on RI# input (default).
Logic 1 = The RI# input has changed from a LOW to a HIGH, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit [3]).
MSR[1]: Delta DSR# Input Flag
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit [3]).
MSR[0]: Delta CTS# Input Flag
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit [3]).
4.11
Modem Status Register (MSR) - Write Only
The upper four bits [7:4] of this register set the delay in number of bits time for the auto RS-485 turn around
from transmit to receive.
MSR [7:4]: Auto RS485 Turn-Around Delay (requires EFR bit [4]=1)
When Auto RS485 feature is enabled (FCTR bit [5]=1) and RTS#/DTR# output is connected to the enable input
of a RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the
last transmitted character. This delay controls when to change the state of RTS#/DTR# output. This delay is
very useful in long-cable networks. Table 18 shows the selection. The bits are enabled by EFR bit-4.
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